Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33554
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/1
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index f83d5db..b0ca79f 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -39,5 +39,5 @@ subdirs-y += ../turbo subdirs-y += ../common
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 451df6e..caeab56 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -4,4 +4,4 @@ subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index eec544d..a1f2d0d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 39246c0..f494e9b 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -23,7 +23,7 @@ ramstage-y += stage_cache.c postcar-y += stage_cache.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..78a6283 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -28,8 +28,8 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 05ea68e..c1f471c 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -16,4 +16,4 @@
ramstage-y += model_65x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 219a0d2..ef68df4 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -16,4 +16,4 @@
ramstage-y += model_67x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 7e09dc6..95aacb3 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -17,4 +17,4 @@ ramstage-y += model_68x_init.c subdirs-y += ../../x86/name
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 81e64e3..84f4ff0 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,4 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 46ae7c7..cef2b0b 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-y += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 9564bf9..9121e3b 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,4 @@ ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 3ac510f..b2f87ab 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_6xx_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-06-*) diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 589e49e..9bb5dca 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_f2x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 19b2e93..ed1eb5f 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 6fbc9ae..196d63e 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fd1603..4fc16d5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -177,10 +177,10 @@
ifeq ($(CONFIG_SOC_INTEL_GLK),y) # Gemini Lake B0 (706a1) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_706ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) else # Apollo Lake 506c2, B0 (506c9) and E0 (506ca) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*) endif
endif # if CONFIG_SOC_INTEL_APOLLOLAKE diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1328944..239004b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -91,9 +91,9 @@ endif
# Coffeelake U43e D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-86-*) # Coffeelake H/S/E3 B0 U0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-96-*)
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 0a23170..e8a3189 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -39,6 +39,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_5066x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*)
endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index e9f555f..9237188 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -83,13 +83,13 @@
# Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4e-*) # Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5e-*) # Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-8e-*) # Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-9e-*) # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples.
Hello Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#3).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/3
Hello Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#4).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/4
Hello Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#5).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 42 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/5
Hello Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#6).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 47 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/6
Hello Subrata Banik, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#7).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 47 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/7
Hello Subrata Banik, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#9).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 20 files changed, 49 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/9
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 9: Code-Review+2
Hello Subrata Banik, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#10).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 20 files changed, 44 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/10
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 11: Code-Review+2
Hello Subrata Banik, John Zhao, Bora Guvendik, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#12).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 20 files changed, 44 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/12
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12: Code-Review+2
Looks like a rebase, Gerrit?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12:
Arthur, is this current, safe to merge?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12:
Patch Set 12:
Arthur, is this current, safe to merge?
I didn't check if all previous steppings + pf are also in this blob repo. Should I check it or do we just trust it?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12:
Arthur, is this current, safe to merge?
I didn't check if all previous steppings + pf are also in this blob repo. Should I check it or do we just trust it?
As we don't guarantee for any configuration that the necessary MCUs are provided, I would say this is a best effort service. IMO, would be nice to check, but you don't have to.
We could also try to write a script that checks if the release notes are true ;)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12:
Patch Set 12:
Arthur, is this current, safe to merge?
I didn't check if all previous steppings + pf are also in this blob repo. Should I check it or do we just trust it?
As we don't guarantee for any configuration that the necessary MCUs are provided, I would say this is a best effort service. IMO, would be nice to check, but you don't have to.
We could also try to write a script that checks if the release notes are true ;)
A tool to find and print the header info of all included MCU would be quite nice indeed.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 12:
https://gitlab.com/iucode-tool/iucode-tool can print out the stuff needed. I'll compare before I'll merge this.
Hello Subrata Banik, John Zhao, Bora Guvendik, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33554
to look at the new patch set (#13).
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328
new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 20 files changed, 44 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/13
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 13: Code-Review+2
(2 comments)
https://review.coreboot.org/#/c/33554/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33554/13//COMMIT_MSG@20 PS13, Line 20: MCU `MCUs` ?
https://review.coreboot.org/#/c/33554/13//COMMIT_MSG@20 PS13, Line 20: are get just `get`
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span multiple targets.
Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products.
The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328
new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 20 files changed, 44 insertions(+), 28 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index fa467e5..72f66ef 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -43,5 +43,5 @@ subdirs-y += ../turbo subdirs-y += ../common
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 451df6e..caeab56 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -4,4 +4,4 @@ subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index eec544d..a1f2d0d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 39246c0..f494e9b 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -23,7 +23,7 @@ ramstage-y += stage_cache.c postcar-y += stage_cache.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..78a6283 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -28,8 +28,8 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 05ea68e..c1f471c 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -16,4 +16,4 @@
ramstage-y += model_65x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 219a0d2..ef68df4 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -16,4 +16,4 @@
ramstage-y += model_67x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 7e09dc6..95aacb3 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -17,4 +17,4 @@ ramstage-y += model_68x_init.c subdirs-y += ../../x86/name
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 81e64e3..84f4ff0 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,4 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 46ae7c7..cef2b0b 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-y += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 9564bf9..9121e3b 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,4 @@ ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 3ac510f..b2f87ab 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_6xx_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-06-*) diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 589e49e..9bb5dca 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_f2x_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 19b2e93..ed1eb5f 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 6fbc9ae..196d63e 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fd1603..4fc16d5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -177,10 +177,10 @@
ifeq ($(CONFIG_SOC_INTEL_GLK),y) # Gemini Lake B0 (706a1) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_706ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) else # Apollo Lake 506c2, B0 (506c9) and E0 (506ca) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*) endif
endif # if CONFIG_SOC_INTEL_APOLLOLAKE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 679efce..37e42f3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -16,6 +16,7 @@ config SOC_INTEL_CANNONLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select MICROCODE_BLOB_NOT_IN_BLOB_REPO help Intel Cannonlake support
@@ -34,6 +35,7 @@ config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select MICROCODE_BLOB_UNDISCLOSED help Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 5017410..8a4a8b7 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -90,10 +90,24 @@ verstage-y += gpio.c endif
-# Coffeelake U43e D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin -# Coffeelake H/S/E3 B0 U0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +# Not yet in intel-microcode repo +#cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*) +else ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0c +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0d +else +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a +endif +else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c +else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) +# TODO +endif
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 0a23170..e8a3189 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -39,6 +39,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_5066x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*)
endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 985acdf..25dce05 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -83,14 +83,14 @@
ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) # Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 # Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09 else # Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 # Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 14:
looking at the soc/skylake/Makefile entry for KBL H0/Y0, the old microcode file (in blobs) contained ucodes for 0806E9/C0 and 0806EA/C0, but the new one contains 0806E9/C0 and 0806E9/10. So we just added support for KBL-Y but dropped support for KBL-R.
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 14:
This breaks my X210, which has an Kaby Lake-R engineering sample. On boot I get "CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7ab0ffe6 - Halting". Reverting this commit gets things working again.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 14:
Patch Set 14:
This breaks my X210, which has an Kaby Lake-R engineering sample. On boot I get "CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7ab0ffe6 - Halting". Reverting this commit gets things working again.
https://review.coreboot.org/c/coreboot/+/34000 possible fixes it. It looks like Kaby Lake-R has the same CPUID as Coffeelake-U...
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 14:
Patch Set 14:
Patch Set 14:
This breaks my X210, which has an Kaby Lake-R engineering sample. On boot I get "CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7ab0ffe6 - Halting". Reverting this commit gets things working again.
https://review.coreboot.org/c/coreboot/+/34000 possible fixes it. It looks like Kaby Lake-R has the same CPUID as Coffeelake-U...
That makes sense. KBL-R is already a 8th gen, same as Coffeelake. Only the naming is confusing.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33554 )
Change subject: Use 3rdparty/intel-microcode ......................................................................
Patch Set 14:
Of course, Coffeelake microarchitecture has 8th Gen and 9th Gen processors. At least according to Intel ARK: https://ark.intel.com/content/www/us/en/ark/products/codename/97787/coffee-l...
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Arthur Heymans (Code Review) -
Matt DeVillier (Code Review)
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Matthew Garrett (Code Review)
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Michał Żygowski (Code Review)
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Nico Huber (Code Review)