Change in ...coreboot[master]: mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode up...

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33939

Change subject: mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update
......................................................................

mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update

Add a region RW_UCODE_STAGED, which will hold the rw microcode
which inturn will be referenced by the FIT in top swap bootblock

Add a region RW_UPDATE_STATE, to hold the firmware update state

Change-Id: Ia44eb00123c0b8c0fcb9a2c540e5bc3660cfa38f
Signed-off-by: Rizwan Qureshi 
---
M src/mainboard/google/hatch/chromeos.fmd
1 file changed, 13 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33939/1

diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index 393ac80..1a5f204 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -8,28 +8,29 @@
    	# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
    	# SPI flash only the top 16MiB actually gets memory mapped.
    	RW_LEGACY(CBFS)@0x0 0x1000000
-		RW_SECTION_A@0x1000000 0x3e0000 {
+		RW_SECTION_A@0x1000000 0x3b0000 {
    		VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x3cffc0
-			RW_FWID_A@0x3dffc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x39ffc0
+			RW_FWID_A@0x3affc0 0x40
    	}
-		RW_SECTION_B@0x13e0000 0x3e0000 {
+		RW_SECTION_B@0x13b0000 0x3b0000 {
    		VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x3cffc0
-			RW_FWID_B@0x3dffc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x39ffc0
+			RW_FWID_B@0x3affc0 0x40
    	}
-		RW_MISC@0x17c0000 0x40000 {
-			UNIFIED_MRC_CACHE@0x0 0x30000 {
+		RW_MISC@0x1760000 0xa0000 {
+			RW_UCODE_STAGED(PRESERVE)@0x0 0x60000
+			UNIFIED_MRC_CACHE@0x60000 0x30000 {
    			RECOVERY_MRC_CACHE@0x0 0x10000
    			RW_MRC_CACHE@0x10000 0x20000
    		}
-			RW_ELOG(PRESERVE)@0x30000 0x4000
-			RW_SHARED@0x34000 0x4000 {
+			RW_ELOG(PRESERVE)@0x90000 0x4000
+			RW_SHARED@0x94000 0x4000 {
    			SHARED_DATA@0x0 0x2000
    			VBLOCK_DEV@0x2000 0x2000
    		}
-			RW_VPD(PRESERVE)@0x38000 0x2000
-			RW_NVRAM(PRESERVE)@0x3a000 0x6000
+			RW_VPD(PRESERVE)@0x98000 0x2000
+			RW_NVRAM(PRESERVE)@0x9a000 0x6000
    	}
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.

[Rizwan Qureshi (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33939

to look at the new patch set (#2).

Change subject: mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update
......................................................................

mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update

Add a region RW_UCODE_STAGED, which will hold the rw microcode
which inturn will be referenced by the FIT in top swap bootblock

Add a region RW_UPDATE_STATE, to hold the firmware update state

Change-Id: Ia44eb00123c0b8c0fcb9a2c540e5bc3660cfa38f
Signed-off-by: Rizwan Qureshi 
---
M src/mainboard/google/hatch/chromeos-16MiB.fmd
M src/mainboard/google/hatch/chromeos.fmd
2 files changed, 21 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33939/2