coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t
by HAOUAS Elyes (Code Review) 08 Jul '19

08 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33804 Change subject: cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t ...................................................................... cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33804/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index b3ffb3d..fb5c5f3 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -185,7 +185,7 @@ void *stacks_top; size_t size; char *base; - int i; + size_t i; struct smm_stub_params *stub_params; struct rmodule smm_stub; -- To view, visit https://review.coreboot.org/c/coreboot/+/33804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32 Gerrit-Change-Number: 33804 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch/x86/acpigen: Compare dev_states_count to size_t
by HAOUAS Elyes (Code Review) 08 Jul '19

08 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33803 Change subject: src/arch/x86/acpigen: Compare dev_states_count to size_t ...................................................................... src/arch/x86/acpigen: Compare dev_states_count to size_t Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33803/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 74cd25a..f9af102 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1115,7 +1115,7 @@ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, const char *dev_states[], size_t dev_states_count) { - int i; + size_t i; for (i = 0; i < dev_states_count; i++) { acpigen_write_name(dev_states[i]); acpigen_write_package(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/33803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa Gerrit-Change-Number: 33803 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qemu-q35: die if started on wrong machine
by Patrick Rudolph (Code Review) 08 Jul '19

08 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31425 Change subject: qemu-q35: die if started on wrong machine ...................................................................... qemu-q35: die if started on wrong machine The QEMU machine "PC" doesn't support MCFG. Die in bootblock if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31425/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 18a083d..96d3457 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -14,6 +14,7 @@ #include <arch/io.h> #include <bootblock_common.h> #include <southbridge/intel/i82801ix/i82801ix.h> +#include <console/console.h> /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,6 +40,11 @@ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* MCFG is now active. If it's not qemu was started for machine PC */ + if (pci_read_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1)) + die("You must run qemu for machine Q35"); } static void enable_spi_prefetch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Gerrit-Change-Number: 31425 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/oprom: Fix coding standard problem from // to /* */
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33783 Change subject: device/oprom: Fix coding standard problem from // to /* */ ...................................................................... device/oprom: Fix coding standard problem from // to /* */ Change-Id: I321d9e54fee42cd9f0cff5f962246934209577f7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/oprom/realmode/x86.c 1 file changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33783/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1..80455a5 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -104,9 +104,9 @@ printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); - x86_exception(regs); // Call coreboot exception handler + x86_exception(regs); /* Call coreboot exception handler */ - return 0; // Never really returns + return 0; /* Never really returns */ } static int intXX_unknown_handler(void) @@ -238,9 +238,9 @@ static u8 vbe_set_mode(vbe_mode_info_t * mi) { printk(BIOS_DEBUG, "VBE: Setting VESA mode %04x\n", mi->video_mode); - // request linear framebuffer mode + /* request linear framebuffer mode */ mi->video_mode |= (1 << 14); - // request clearing of framebuffer + /* request clearing of framebuffer */ mi->video_mode &= ~(1 << 15); realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, 0x0000, 0x0000, 0x0000, 0x0000); @@ -393,8 +393,9 @@ ip, cs, flags); #endif - // Fetch arguments from the stack and put them to a place - // suitable for the interrupt handlers + /* Fetch arguments from the stack and put them to a place + * suitable for the interrupt handlers + */ X86_EAX = eax; X86_ECX = ecx; X86_EDX = edx; @@ -409,15 +410,16 @@ X86_CS = cs; X86_EFLAGS = flags; - // Call the interrupt handler for this int# + /* Call the interrupt handler for this int# */ ret = intXX_handler[intnumber](); - // Put registers back on the stack. The assembler code - // will later pop them. - // What happens here is that we force (volatile!) changing - // the values of the parameters of this function. We do this - // because we know that they stay alive on the stack after - // we leave this function. Don't say this is bollocks. + /* Put registers back on the stack. The assembler code + * will later pop them. + * What happens here is that we force (volatile!) changing + * the values of the parameters of this function. We do this + * because we know that they stay alive on the stack after + * we leave this function. Don't say this is bollocks. + */ *(volatile u32 *)&eax = X86_EAX; *(volatile u32 *)&ecx = X86_ECX; *(volatile u32 *)&edx = X86_EDX; @@ -428,10 +430,10 @@ /* Pass success or error back to our caller via the CARRY flag */ if (ret) { - flags &= ~1; // no error: clear carry + flags &= ~1; /* no error: clear carry */ }else{ printk(BIOS_DEBUG,"int%02x call returned error.\n", intnumber); - flags |= 1; // error: set carry + flags |= 1; /* error: set carry */ } *(volatile u16 *)&stackflags = flags; -- To view, visit https://review.coreboot.org/c/coreboot/+/33783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I321d9e54fee42cd9f0cff5f962246934209577f7 Gerrit-Change-Number: 33783 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/oprom: Update vbe_info_t as per vbe specification 3.0
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33806 Change subject: device/oprom: Update vbe_info_t as per vbe specification 3.0 ...................................................................... device/oprom: Update vbe_info_t as per vbe specification 3.0 This patch fixes unable to get correct value from TotalMemory variable using existing vbe_info_t structure. New vbe_info_t structure follows vbe spec 3.0. http://www.vesa.org/public/VBE/vbe3.pdf Change-Id: I12db01280aec480f1f42332ebe97d92539dfdc1c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/oprom/yabel/vbe.c M src/include/vbe.h 2 files changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33806/1 diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 682bf00..104b4c2 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -66,6 +66,9 @@ u8 *biosmem; u32 biosmem_size; +/* Let's hope we never have more than 256 video modes. */ +#define MAX_VBE_FRAMEBUFFER_MODE 256 + #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static inline u8 vbe_prepare(void) @@ -133,20 +136,9 @@ info->capabilities = in32le(vbe_info_buffer + 10); // offset 14: 32 bit le containing segment:offset of supported video mode table - u16 *video_mode_ptr; - video_mode_ptr = - (u16 *) (biosmem + - ((in16le(vbe_info_buffer + 16) << 4) + - in16le(vbe_info_buffer + 14))); - u32 i = 0; - do { - info->video_mode_list[i] = in16le(video_mode_ptr + i); - i++; - } - while ((i < - (sizeof(info->video_mode_list) / - sizeof(info->video_mode_list[0]))) - && (info->video_mode_list[i - 1] != 0xFFFF)); + info->video_mode_ptr = + (u32 *)(biosmem + ((in16le(vbe_info_buffer + 16) << 4) + + in16le(vbe_info_buffer + 14))); //offset 18: 16bit le total memory in 64KB blocks info->total_memory = in16le(vbe_info_buffer + 18); @@ -441,7 +433,7 @@ vbe_get_info(void) { u8 rval; - int i; + int i = 0; // XXX FIXME these need to be filled with sane values @@ -536,12 +528,17 @@ DEBUG_PRINTF_VBE("DDC: found display type %d\n", output->display_type); memcpy(output->edid_block_zero, ddc_info.edid_block_zero, sizeof(ddc_info.edid_block_zero)); - i = 0; vbe_mode_info_t mode_info; vbe_mode_info_t best_mode_info; + u16 video_mode_list[MAX_VBE_FRAMEBUFFER_MODE]; // initialize best_mode to 0 memset(&best_mode_info, 0, sizeof(best_mode_info)); - while ((mode_info.video_mode = info.video_mode_list[i]) != 0xFFFF) { + do { + video_mode_list[i] = in16le(info.video_mode_ptr + i); + i++; + } while (video_mode_list[i - 1] != 0xFFFF); + i = 0; + while ((mode_info.video_mode = video_mode_list[i]) != 0xFFFF) { //DEBUG_PRINTF_VBE("%x: Mode: %04x\n", i, mode_info.video_mode); vbe_get_mode_info(&mode_info); diff --git a/src/include/vbe.h b/src/include/vbe.h index 2aa45a8..af7bfa1 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -41,9 +41,9 @@ u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... + u32 *video_mode_ptr; u16 total_memory; + char reserved[236]; } __packed vbe_info_t; typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/33806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12db01280aec480f1f42332ebe97d92539dfdc1c Gerrit-Change-Number: 33806 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vbe.h: Convert hardcode vega mode into macro
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33782 Change subject: vbe.h: Convert hardcode vega mode into macro ...................................................................... vbe.h: Convert hardcode vega mode into macro This patch replaces vega framebuffer mode hard coded value into macro (MAX_VBE_FRAMEBUFFER_MODE). Also make use of __packed to align data access. Change-Id: I5e79b21acf44f6ca184a09d42acdf69c31dd4841 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/vbe.h 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33782/1 diff --git a/src/include/vbe.h b/src/include/vbe.h index 2c40d05..88888e8 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -14,6 +14,10 @@ #define VBE_H #include <boot/coreboot_tables.h> + +/* Let's hope we never have more than 256 video modes. */ +#define MAX_VBE_FRAMEBUFFER_MODE 256 + // these structs are for input from and output to OF typedef struct { u8 display_type; // 0 = NONE, 1 = analog, 2 = digital @@ -41,10 +45,9 @@ u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... + u16 video_mode_list[MAX_VBE_FRAMEBUFFER_MODE]; u16 total_memory; -} vbe_info_t; +} __packed vbe_info_t; typedef struct { u16 mode_attributes; // 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e79b21acf44f6ca184a09d42acdf69c31dd4841 Gerrit-Change-Number: 33782 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/external/Memtest86Plus: update to version 002 stable
by Martin Kepplinger (Code Review) 08 Jul '19

08 Jul '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32613 Change subject: payloads/external/Memtest86Plus: update to version 002 stable ...................................................................... payloads/external/Memtest86Plus: update to version 002 stable The memtest86plus project has been tagged as stable. Update the coreboot build accordingly. Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M payloads/external/Memtest86Plus/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32613/1 diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 4b3132d..b799f9e 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -15,7 +15,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master NAME-$(CONFIG_MEMTEST_MASTER)=Master -TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb +TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 NAME-$(CONFIG_MEMTEST_STABLE)=Stable TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/32613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Gerrit-Change-Number: 32613 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen
by Frank Wu (Code Review) 08 Jul '19

08 Jul '19

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33808 Change subject: mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen ...................................................................... mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/33808/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index e309175..e92d93b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -195,8 +195,8 @@ PAD_NC(GPP_D7, NONE), /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), - /* D9 : GPP_D9 ==> NC */ - PAD_NC(GPP_D9, NONE), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* D10 : GPP_D10 ==> NC */ PAD_NC(GPP_D10, NONE), /* D11 : GPP_D11 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index d676843..fd2d061 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -91,6 +91,8 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 373438c..c3a1b2e 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -82,6 +82,8 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/33808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33140869990aa4715c780b0fa322921e450530ef Gerrit-Change-Number: 33808 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Update GPIO settings
by Krishna P Bhat D (Code Review) 08 Jul '19

08 Jul '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32176 Change subject: mb/google/hatch: Update GPIO settings ...................................................................... mb/google/hatch: Update GPIO settings This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Disable I2C #2 in devicetree. 3. Set GPP_B19, GPP_G7 to NF1. BUG=b:123907904 Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32176/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 4d1c87e..10f851b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -106,8 +106,8 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GPP_B19 ==> NC */ - PAD_NC(GPP_B19, NONE), + /* B19 : Set to NF1 */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : PCH_SPI_FPMCU_CLK_R */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* B21 : PCH_SPI_FPMCU_MISO */ @@ -329,21 +329,21 @@ PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, DN_20K), + /* G7 : Set to NF1 */ + PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* * H0 : HP_INT_L diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..57daba2 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -69,7 +69,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..098bca6 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -54,7 +54,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/32176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Gerrit-Change-Number: 32176 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: mediatek/mt8183: update dcxo setting
by Weiyi Lu (Code Review) 07 Jul '19

07 Jul '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32323 to review the following change. Change subject: WIP: mediatek/mt8183: update dcxo setting ...................................................................... WIP: mediatek/mt8183: update dcxo setting Disable unused DCXO and power mode. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32323/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fe..a721ff8 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -140,6 +140,7 @@ PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..57f26e8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -281,9 +281,10 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); -- To view, visit https://review.coreboot.org/c/coreboot/+/32323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Gerrit-Change-Number: 32323 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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