coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by ...
by Mike Banon (Code Review) 07 Jul '19

07 Jul '19

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33870 Change subject: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware G505S does not have any SAS or NVMe controllers and could not have a TPM, so it makes sense to disable the related SeaBIOS options for this laptop. This reduces the size of compiled SeaBIOS by 129344-110048 = 19296 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c --- M src/mainboard/lenovo/g505s/Kconfig A src/mainboard/lenovo/g505s/config_seabios 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33870/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..b80019e 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,8 @@ string default "1002,990b" +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios new file mode 100644 index 0000000..1959fa3 --- /dev/null +++ b/src/mainboard/lenovo/g505s/config_seabios @@ -0,0 +1,7 @@ +### +### SeaBIOS custom configuration for Lenovo G505S +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c Gerrit-Change-Number: 33870 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: include/cpu/x86/mtrr: Fix return type
by HAOUAS Elyes (Code Review) 07 Jul '19

07 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33817 Change subject: include/cpu/x86/mtrr: Fix return type ...................................................................... include/cpu/x86/mtrr: Fix return type Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/mtrr.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33817/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 49ed462..29256c8 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -120,7 +120,7 @@ /* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { - int r; + unsigned int r; __asm__("bsrl %1,%0\n\t" "jnz 1f\n\t" @@ -132,7 +132,7 @@ /* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { - int r; + unsigned int r; __asm__("bsfl %1,%0\n\t" "jnz 1f\n\t" -- To view, visit https://review.coreboot.org/c/coreboot/+/33817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Gerrit-Change-Number: 33817 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: soc/amd/picasso: Remove all AGESA references
by Marshall Dawson (Code Review) 06 Jul '19

06 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33755 Change subject: soc/amd/picasso: Remove all AGESA references ...................................................................... soc/amd/picasso: Remove all AGESA references Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/southbridge.c 9 files changed, 11 insertions(+), 277 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33755/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 33aae26..a930f60 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,8 +49,6 @@ select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -106,18 +104,6 @@ int default 48 -config BOTTOMIO_POSITION - hex "Bottom of 32-bit IO space" - default 0xD0000000 - help - If PCI peripherals with big BARs are connected to the system - the bottom of the IO must be decreased to allocate such - devices. - - Declare the beginning of the 128MB-aligned MMIO region. This - option is useful when PCI peripherals requesting large address - ranges are present. - config MMCONF_BASE_ADDRESS hex default 0xF8000000 @@ -199,7 +185,7 @@ bool "System is legacy free" help Select y if there is no keyboard controller in the system. - This sets variables in AGESA and ACPI. + This sets a variable in ACPI. config SERIRQ_CONTINUOUS_MODE bool @@ -213,7 +199,6 @@ default 0x400 help Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. config PICASSO_UART bool "UART controller on Picasso" diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 6dc47cd..249be98 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,9 +25,6 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> - #include "chip.h" /* Supplied by i2c.c */ @@ -152,19 +149,3 @@ .init = soc_init, .final = soc_final }; - -static void earliest_ramstage(void *unused) -{ - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { - post_code(0x47); - do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); - } else { - /* Complete the initial system restoration */ - post_code(0x46); - do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); - } -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ff9c845..39c7026 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -23,33 +23,9 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> -#define MAX_NODES 1 -#define MAX_DRAM_CH 1 -#define MAX_DIMMS_PER_CH 2 - #define PICASSO_I2C_DEV_MAX 4 struct soc_amd_picasso_config { - u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; - enum { - DRAM_CONTENTS_KEEP, - DRAM_CONTENTS_CLEAR - } dram_clear_on_reset; - - enum { - /* Do not enable UMA in the system. */ - UMAMODE_NONE, - /* Enable UMA with a specific size. */ - UMAMODE_SPECIFIED_SIZE, - /* Let AGESA determine the proper size. Non-legacy requires - * the resolution to be specified PLATFORM_CONFIGURATION */ - UMAMODE_AUTO_LEGACY, - UMAMODE_AUTO_NON_LEGACY, - } uma_mode; - - /* Used if UMAMODE_SPECIFIED_SIZE is set. */ - size_t uma_size; - /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. @@ -60,18 +36,6 @@ */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; - u8 stapm_percent; - u32 stapm_time_ms; - u32 stapm_power_mw; - /* - * This specifies the LVDS/eDP power-up sequence time for the delay - * between VaryBL and BLON. - * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. - * n - Values other than zero specify a setting of (4 * n) milliseconds - * time delay. - */ - u8 lvds_poseq_varybl_to_blon; - u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7d47645..7bc1810 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,16 +18,8 @@ #include <device/device.h> -/* - * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest - * numbered registers. Any values defined below are subtracted from the - * highest numbered registers. - * - * todo: Revisit this once AGESA no longer programs MTRRs. - */ #define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_CAR_HEAP 2 -#define SOC_EARLY_VMTRR_TEMPRAM 3 +#define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index f7df277..65705b9 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -110,6 +110,8 @@ SMM_SUBREGION_NUM, }; +void amd_initcpuio(void); + /* * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 9e2b901..6733946 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -326,7 +326,7 @@ void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** - * @brief Save the UMA bize returned by AGESA + * @brief Save the UMA bize * * @param size = in bytes * @@ -334,7 +334,7 @@ */ void save_uma_size(uint32_t size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Save the UMA base address * * @param base = 64bit base address * diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 5985832..cace626 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -27,9 +27,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <romstage_handoff.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> -#include <agesa_headers.h> #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -188,6 +185,7 @@ return current; } +#if 0 /* TODO - different mechanism to collect this info for Family 17h */ static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -207,6 +205,7 @@ return (unsigned long)current; } +#endif static void northbridge_fill_ssdt_generator(struct device *device) { @@ -233,6 +232,7 @@ unsigned long current, acpi_rsdp_t *rsdp) { +#if 0 /* TODO - different mechanism to collect this info for Family 17h */ acpi_srat_t *srat; acpi_slit_t *slit; acpi_header_t *ssdt; @@ -333,6 +333,7 @@ acpi_add_table(rsdp, ssdt); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); +#endif return current; } @@ -401,9 +402,7 @@ void domain_enable_resources(struct device *dev) { - /* Must be called after PCI enumeration and resource allocation */ - if (!romstage_handoff_is_resume()) - do_agesawrapper(AMD_INIT_MID, "amdinitmid"); + /* TODO: placeholder for FSP call */ } void domain_set_resources(struct device *dev) @@ -474,19 +473,3 @@ return new_vendev; } - -__weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } - -void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) -{ - const struct device *dev = SOC_IOMMU_DEV; - params->IommuSupport = dev && dev->enabled; - set_board_env_params(params); -} - -void SetNbMidParams(GNB_MID_CONFIGURATION *params) -{ - /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ - params->iGpuVgaMode = 0; - params->GnbIoapicAddress = IO_APIC2_ADDR; -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 904f556..950b41f 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -27,8 +27,6 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/southbridge.h> @@ -40,22 +38,6 @@ /* By default, don't do anything */ } -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -63,58 +45,20 @@ void *smm_base; size_t smm_size; uintptr_t tseg_base; - msr_t base, mask; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); - int i; console_init(); mainboard_romstage_entry(s3_resume); - bsp_agesa_call(); - if (!s3_resume) { post_code(0x40); - do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - post_code(0x41); - /* - * TODO: This is a hack to work around current AGESA behavior. - * AGESA needs to change to reflect that coreboot owns - * the MTRRs. - * - * After setting up DRAM, AGESA also completes the configuration - * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be - * in cache and lost. For now, set the regions UC to ensure - * the writes get to DRAM. - */ - for (i = 0 ; i < vmtrrs ; i++) { - base = rdmsr(MTRR_PHYS_BASE(i)); - mask = rdmsr(MTRR_PHYS_MASK(i)); - if (!(mask.lo & MTRR_PHYS_MASK_VALID)) - continue; - - if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { - base.lo &= ~0x7; - base.lo |= MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_PHYS_BASE(i), base); - } - } - /* Disable WB from to region 4GB-TOM2. */ - msr_t sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; - wrmsr(SYSCFG_MSR, sys_cfg); if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - - post_code(0x61); } post_code(0x43); @@ -155,64 +99,3 @@ post_code(0x50); /* Should never see this post code. */ } - -void SetMemParams(AMD_POST_PARAMS *PostParams) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); - /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? - UMA_AUTO : UMA_NONE; - return; - } - - cfg = dev->chip_info; - - PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; - - switch (cfg->uma_mode) { - case UMAMODE_NONE: - PostParams->MemConfig.UmaMode = UMA_NONE; - break; - case UMAMODE_SPECIFIED_SIZE: - PostParams->MemConfig.UmaMode = UMA_SPECIFIED; - /* 64 KiB blocks. */ - PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); - break; - case UMAMODE_AUTO_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_LEGACY; - break; - case UMAMODE_AUTO_NON_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; - break; - } -} - -void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct _PLATFORM_CONFIGURATION *platform; - - if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" - " config, STAPM unchanged\n"); - return; - } - cfg = dev->chip_info; - platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && - (cfg->stapm_power_mw)) { - platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; - platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time_ms; - platform->PkgPwrLimitDC = cfg->stapm_power_mw; - platform->PkgPwrLimitAC = cfg->stapm_power_mw; - platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; - } -} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index dca3591..d0e12a9 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> -#include <amdblocks/agesawrapper.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> @@ -34,7 +33,6 @@ #include <soc/amd_pci_int_defs.h> #include <delay.h> #include <soc/pci_devs.h> -#include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> @@ -54,60 +52,6 @@ { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } }; -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) - || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataAhci == CONFIG_PICASSO_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_PICASSO_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME * provides a visible association with the index, therefore helping -- To view, visit https://review.coreboot.org/c/coreboot/+/33755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Gerrit-Change-Number: 33755 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: mediatek/mt8183: Enable RTC eosc calibration feature to save power
by Ran Bi (Code Review) 06 Jul '19

06 Jul '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32339 Change subject: mediatek/mt8183: Enable RTC eosc calibration feature to save power ...................................................................... mediatek/mt8183: Enable RTC eosc calibration feature to save power When system shutdown, RTC enable eosc calibration feature to save power. Then coreboot RTC driver need to call rtc_enable_dcxo function at every boot up to switch RTC clock source to a more accurate one. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32339/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..ba05f86 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -197,12 +197,6 @@ goto err; } - /* using dcxo 32K clock */ - if (!rtc_enable_dcxo()) { - ret = -RTC_STATUS_OSC_SETTING_FAIL; - goto err; - } - if (recover) mdelay(20); @@ -311,6 +305,10 @@ pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + /* using dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() fail\n"); + rtc_boot_common(); rtc_bbpu_power_on(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Gerrit-Change-Number: 32339 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

6 16

Change in ...coreboot[master]: test
by HAOUAS Elyes (Code Review) 05 Jul '19

05 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33672 Change subject: test ...................................................................... test Change-Id: I1eb58673e1737d91af8cf20a128bcaa58d690275 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/chromeec M 3rdparty/fsp M 3rdparty/libgfxinit 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33672/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d diff --git a/3rdparty/fsp b/3rdparty/fsp index 1d2b7e1..5996417 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index b3b9fa3..d49b56b 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit b3b9fa34bb99d33d0fc6a69c64966a71cebd5bd6 +Subproject commit d49b56baf97136e1b65f032a985291bf40a73260 -- To view, visit https://review.coreboot.org/c/coreboot/+/33672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb58673e1737d91af8cf20a128bcaa58d690275 Gerrit-Change-Number: 33672 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci_rom.c: Fix indent for 'if' statement and remove unneeded '...
by HAOUAS Elyes (Code Review) 05 Jul '19

05 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33330 Change subject: device/pci_rom.c: Fix indent for 'if' statement and remove unneeded 'else' ...................................................................... device/pci_rom.c: Fix indent for 'if' statement and remove unneeded 'else' 'else' is not needed after a 'break' or 'return'. Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_rom.c 1 file changed, 21 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33330/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 2dbfb51..f1f6c41 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -56,32 +56,31 @@ printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else if (!CONFIG(ON_DEVICE_ROM_LOAD)) { - printk(BIOS_DEBUG, "PCI Option ROM loading disabled " - "for %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "PCI Option ROM loading disabled " + "for %s\n", dev_path(dev)); + return NULL; + } + uintptr_t rom_address; + + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { +#if CONFIG(BOARD_EMULATION_QEMU_X86) + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) + rom_address = 0xc0000; + else +#endif return NULL; } else { - uintptr_t rom_address; - - rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - - if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG(BOARD_EMULATION_QEMU_X86) - if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) - rom_address = 0xc0000; - else -#endif - return NULL; - } else { - /* Enable expansion ROM address decoding. */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); - } - - printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", - dev_path(dev), (unsigned long)rom_address); - rom_header = (struct rom_header *)rom_address; + /* Enable expansion ROM address decoding. */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); } + printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", + dev_path(dev), (unsigned long)rom_address); + rom_header = (struct rom_header *)rom_address; + printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, " "INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), -- To view, visit https://review.coreboot.org/c/coreboot/+/33330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Gerrit-Change-Number: 33330 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake/romstage: Increase size of postcar stack
by Mario Scheithauer (Code Review) 04 Jul '19

04 Jul '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33775 Change subject: soc/intel/apollolake/romstage: Increase size of postcar stack ...................................................................... soc/intel/apollolake/romstage: Increase size of postcar stack If you currently activate the measured boot on an Apollo Lake mainboard, you will run into a stack overflow during postcar. Such a behavior has already been observed on the Sky Lake platform and a corresponding patch has been made for this (https://review.coreboot.org/c/coreboot/+/33434). This issue occurs since the patch for the correct timestamp value in postcar comes up (https://review.coreboot.org/c/coreboot/+/32726 and https://review.coreboot.org/c/coreboot/+/32881). By increasing the stack size for postcar the issue is solved. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33775/1 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5bf501d..da8e581 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -240,7 +240,7 @@ else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 2*KiB)) die("Unable to initialize postcar frame.\n"); mainboard_save_dimm_info(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Gerrit-Change-Number: 33775 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Adjust postcar MTRRs
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33927 Change subject: drivers/intel/fsp1_1: Adjust postcar MTRRs ...................................................................... drivers/intel/fsp1_1: Adjust postcar MTRRs Use of romstage_ram_stack_bottom() was invalid, it potentially uses a different ROMSTAGE_RAM_STACK_SIZE from the postcar_frame_init() call. If alignment evaluated to 1 MiB, that WB MTRR may not have covered all of CBMEM range, having some impact on boot speeds. There is no need to accurately describe write-back MTRR ranges for postcar. Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 7 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33927/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index bd3f478..b10a410 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,6 +14,7 @@ */ #include <arch/symbols.h> +#include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/intel/romstage.h> @@ -32,8 +33,7 @@ void platform_enter_postcar(void) { struct postcar_frame pcf; - size_t alignment; - uint32_t aligned_ram; + uintptr_t top_of_ram; if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -44,53 +44,12 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. */ - - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By - * setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, - MTRR_TYPE_WRBACK); - } + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Gerrit-Change-Number: 33927 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Revert "soc/intel/skylake/romstage: Increase size of postcar stack"
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Hello Julius Werner, Arthur Heymans, Patrick Rudolph, Christian Walter, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33585 to review the following change. Change subject: Revert "soc/intel/skylake/romstage: Increase size of postcar stack" ...................................................................... Revert "soc/intel/skylake/romstage: Increase size of postcar stack" This reverts commit f70cb8bf968af75669325104756464ce6f4b824b. Reason for revert: Merged prematurely with some vague argumentation in the commit message. Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33585/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0eff793..2819c6f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -156,7 +156,7 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 8*KiB)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/33585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 Gerrit-Change-Number: 33585 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants/fleex: Enable EMR function for Grob360S
by Chris Zhou (Code Review) 04 Jul '19

04 Jul '19

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33802 Change subject: mb/google/octopus/variants/fleex: Enable EMR function for Grob360S ...................................................................... mb/google/octopus/variants/fleex: Enable EMR function for Grob360S Enable EMR function for Grob360S BUG=b:135968368 BRANCH=octopus TEST=Work normally with I2C6 which HW reworked. Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/fleex/overridetree.cb 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33802/1 diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 89adfb8..330cc02 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -30,7 +30,7 @@ PAD_NC(GPIO_138, UP_20K), PAD_NC(GPIO_139, UP_20K), - PAD_NC(GPIO_140, UP_20K), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* GPIO_140 -- PEN_RESET */ PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), PAD_NC(GPIO_145, UP_20K), diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 19246e0..3050a7b 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -61,6 +61,9 @@ .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 104, @@ -80,7 +83,19 @@ }" device domain 0 on - device pci 16.0 off end # - I2C 0 + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 17.1 on chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/33802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Gerrit-Change-Number: 33802 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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