coreboot-gerrit June 2019

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Change in ...coreboot[master]: util/cbmem: Use correct integer types for loop indices
by Jacob Garber (Code Review) 02 Jul '19

02 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33850 Change subject: util/cbmem: Use correct integer types for loop indices ...................................................................... util/cbmem: Use correct integer types for loop indices Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/cbmem/cbmem.c 1 file changed, 8 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33850/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 52fdc9b..9a443a8 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -543,9 +543,7 @@ static const char *timestamp_name(uint32_t id) { - int i; - - for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { if (timestamp_ids[i].id == id) return timestamp_ids[i].name; } @@ -608,7 +606,6 @@ /* dump the timestamp table */ static void dump_timestamps(int mach_readable) { - int i; const struct timestamp_table *tst_p; struct timestamp_table *sorted_tst_p; size_t size; @@ -656,7 +653,7 @@ sizeof(struct timestamp_entry), compare_timestamp_entries); total_time = 0; - for (i = 0; i < sorted_tst_p->num_entries; i++) { + for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { uint64_t stamp; const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; @@ -685,7 +682,6 @@ /* dump the tcpa log table */ static void dump_tcpa_log(void) { - int i, j; const struct tcpa_table *tclt_p; size_t size; struct mapping tcpa_mapping; @@ -710,12 +706,12 @@ printf("coreboot TCPA log:\n\n"); - for (i = 0; i < tclt_p->num_entries; i++) { + for (uint16_t i = 0; i < tclt_p->num_entries; i++) { const struct tcpa_entry *tce = &tclt_p->entries[i]; printf(" PCR-%u ", tce->pcr); - for (j = 0; j < tce->digest_length; j++) + for (uint32_t j = 0; j < tce->digest_length; j++) printf("%02x", tce->digest[j]); printf(" %s [%s]\n", tce->digest_type, tce->name); @@ -804,9 +800,8 @@ BANNER_REGEX("romstage"), OVERFLOW_REGEX("ramstage"), BANNER_REGEX("ramstage") }; - int i; - for (i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { + for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; assert(!regcomp(&re, regex[i], 0)); @@ -873,7 +868,6 @@ void rawdump(uint64_t base, uint64_t size) { - int i; const uint8_t *m; struct mapping dump_mapping; @@ -881,7 +875,7 @@ if (!m) die("Unable to map rawdump memory\n"); - for (i = 0 ; i < size; i++) + for (uint64_t i = 0 ; i < size; i++) printf("%c", m[i]); unmap_memory(&dump_mapping); @@ -935,12 +929,11 @@ #define MAX_STAGEx 10 void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) { - int i; const char *name; char stage_x[20]; name = NULL; - for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { if (cbmem_ids[i].id == id) { name = cbmem_ids[i].name; break; @@ -1388,11 +1381,10 @@ parse_cbtable(baseaddr, cb_table_size); #else - int j; unsigned long long possible_base_addresses[] = { 0, 0xf0000 }; /* Find and parse coreboot table */ - for (j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { + for (size_t j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { if (!parse_cbtable(possible_base_addresses[j], 0)) break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Gerrit-Change-Number: 33850 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] 3rdparty/fsp: Update submodule pointer
by Bora Guvendik (Code Review) 02 Jul '19

02 Jul '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33642 Change subject: [WIP] 3rdparty/fsp: Update submodule pointer ...................................................................... [WIP] 3rdparty/fsp: Update submodule pointer Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40 Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33642/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 1d2b7e1..5996417 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f -- To view, visit https://review.coreboot.org/c/coreboot/+/33642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Gerrit-Change-Number: 33642 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/: Fix cpu_cpuid_extended_level() returned value
by HAOUAS Elyes (Code Review) 02 Jul '19

02 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33814 Change subject: arch/x86/: Fix cpu_cpuid_extended_level() returned value ...................................................................... arch/x86/: Fix cpu_cpuid_extended_level() returned value Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33814/1 diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 1191227..0fd0af0 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -49,7 +49,7 @@ } #endif -int cpu_cpuid_extended_level(void) +unsigned int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); } diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ff1a33b..75f1f43 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -200,7 +200,7 @@ #define CPUID_CACHE_NO_OF_SETS_MASK 0xffffffff #define CPUID_CACHE_NO_OF_SETS(res) CPUID_CACHE(NO_OF_SETS, (res).ecx) -int cpu_cpuid_extended_level(void); +unsigned int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); void smm_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Gerrit-Change-Number: 33814 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/docker/coreboot.org-status: Add more "nice" names for CPUs
by Patrick Georgi (Code Review) 02 Jul '19

02 Jul '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33930 Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ...................................................................... util/docker/coreboot.org-status: Add more "nice" names for CPUs It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework. Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M util/docker/coreboot.org-status/board-status.html/tohtml.sh 1 file changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33930/1 diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 1992826..41de9ff 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -248,7 +248,12 @@ southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" - cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" + cpu="$(sed -n \ + -e "/ select CPU_/ s, select CPU_,,p" \ + -e "/ select SOC_/ s, select SOC_,,p" \ + "$vendor_board_dir/Kconfig" | \ + grep -v "AMD_AGESA_FAMILY" | \ + grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" @@ -302,12 +307,24 @@ AMD_SC520) cpu_nice="AMD Élan™SC520"; socket_nice="—";; + AMD_STONEYRIDGE_FP4) + cpu_nice="AMD Stoney Ridge"; + socket_nice="FP4 BGA";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; + MEDIATEK_MT8173) + cpu_nice="MediaTek MT8173"; + socket_nice="—";; + NVIDIA_TEGRA124) + cpu_nice="NVIDIA Tegra 124"; + socket_nice="—";; + NVIDIA_TEGRA210) + cpu_nice="NVIDIA Tegra 210"; + socket_nice="—";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; socket_nice="?";; @@ -317,6 +334,42 @@ TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; + IMGTEC_PISTACHIO) + cpu_nice="Imagination Technologies Pistachio"; + socket_nice="—";; + INTEL_APOLLOLAKE) + cpu_nice="Intel® Apollo Lake"; + socket_nice="—";; + INTEL_BAYTRAIL) + cpu_nice="Intel® Bay Trail"; + socket_nice="—";; + INTEL_BRASWELL) + cpu_nice="Intel® Braswell"; + socket_nice="—";; + INTEL_BROADWELL) + cpu_nice="Intel® Broadwell"; + socket_nice="—";; + INTEL_DENVERTON_NS) + cpu_nice="Intel® Denverton-NS"; + socket_nice="—";; + INTEL_FSP_BROADWELL_DE) + cpu_nice="Intel® Broadwell-DE"; + socket_nice="—";; + INTEL_GLK) + cpu_nice="Intel® Gemini Lake"; + socket_nice="—";; + INTEL_ICELAKE) + cpu_nice="Intel® Ice Lake"; + socket_nice="—";; + INTEL_KABYLAKE) + cpu_nice="Intel® Kaby Lake"; + socket_nice="—";; + INTEL_SANDYBRIDGE) + cpu_nice="Intel® Sandy Bridge"; + socket_nice="—";; + INTEL_SKYLAKE) + cpu_nice="Intel® Skylake"; + socket_nice="—";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; socket_nice="Slot 1";; @@ -384,6 +437,24 @@ INTEL_SOCKET_MFCBGA479) cpu_nice="Intel® Mobile Celeron" socket_nice="Socket 479";; + INTEL_WHISKEYLAKE) + cpu_nice="Intel® Whiskey Lake"; + socket_nice="—";; + QC_IPQ806X) + cpu_nice="Qualcomm IPQ806x"; + socket_nice="—";; + QUALCOMM_QCS405) + cpu_nice="Qualcomm QCS405"; + socket_nice="—";; + QUALCOMM_SDM845) + cpu_nice="Qualcomm SDM845"; + socket_nice="—";; + ROCKCHIP_RK3288) + cpu_nice="Rockchip RK3288"; + socket_nice="—";; + ROCKCHIP_RK3399) + cpu_nice="Rockchip RK3399"; + socket_nice="—";; VIA_C3) cpu_nice="VIA C3™"; socket_nice="?" -- To view, visit https://review.coreboot.org/c/coreboot/+/33930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Gerrit-Change-Number: 33930 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/release: add more categories
by Patrick Georgi (Code Review) 02 Jul '19

02 Jul '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33929 Change subject: util/release: add more categories ...................................................................... util/release: add more categories Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M util/release/genrelnotes 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33929/1 diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 9a88b49..e4f304b 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -291,7 +291,7 @@ echo "" >> "$LOGFILE" ### SPECIFIC AREAS FOR RELEASE ### -get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch" +get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch\|remove unused\|remove.*not used" get_log_dedupe "Google Kahlee / AMD Gardenia" "src/mainboard/google/kahlee src/mainboard/amd/gardenia" "kahlee\|gardenia" get_log_dedupe "AMD Stoney Ridge" "src/soc/amd/stoneyridge" "stoney" @@ -329,11 +329,16 @@ get_log_dedupe "Intel Common" "src/soc/intel/common src/southbridge/intel/common src/northbridge/intel/common" "" get_log_dedupe "Amd Common" "src/soc/amd/common src/southbridge/amd/common" "" +get_log_dedupe "Nvidia" "src/southbridge/nvidia" "" +get_log_dedupe "Via" "src/northbridge/via src/southbridge/via" "" +get_log_dedupe "Broadcom" "src/southbridge/broadcom" "" +get_log_dedupe "Qualcomm" "src/soc/qualcomm" "" + get_log_dedupe "Intel vendorcode / FSP" "src/drivers/intel/fsp* src/vendorcode/intel" "" get_log_dedupe "AMD vendorcode / AGESA / PI" "src/vendorcode/amd" "" get_log_dedupe "Google vendorcode" "src/vendorcode/google" -get_log_dedupe "TPM" "src/drivers/i2c/tpm" "tpm" +get_log_dedupe "TPM" "src/drivers/i2c/tpm src/security/tpm" "tpm" get_log_dedupe "Vboot" "src/vboot" "vboot" @@ -394,6 +399,9 @@ "Makefile Makefile.inc toolchain.inc src/Kconfig src/cpu/Makefile.inc" get_log_dedupe "Submodules" "3rdparty util/nvidia/cbootimage" + +get_log_dedupe "Maintainers" "MAINTAINERS" "" + # Finally, get anything that was missed above get_log_dedupe "MISC" "." -- To view, visit https://review.coreboot.org/c/coreboot/+/33929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Gerrit-Change-Number: 33929 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Set trackpad wake to GPP_A21
by Shelley Chen (Code Review) 02 Jul '19

02 Jul '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33820 Change subject: mb/google/hatch: Set trackpad wake to GPP_A21 ...................................................................... mb/google/hatch: Set trackpad wake to GPP_A21 Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb 2 files changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33820/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a4fb4c9..38e31ba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -54,12 +54,8 @@ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : WLAN_INT_L */ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), - /* - * A21 : TRACKPAD_INT_ODL (wake) - * TODO Combine into single gpio, when ITSS IPCx configuration - * is fixed in FSP. - */ - PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), + /* A21 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), /* A23 : FPMCU_PCH_INT_ODL */ @@ -209,12 +205,8 @@ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA_0_SNDW4_DATA */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - /* - * D21 : TRACKPAD_INT_ODL - * TODO Combine into single gpio with invert mode, when ITSS - * IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), + /* D21 : GPP_D22 ==> NC */ + PAD_NC(GPP_D21, NONE), /* D22 : GPP_D22 ==> NC */ PAD_NC(GPP_D22, NONE), /* D23 : SPP_MCLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index d676843..2582940 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -63,7 +63,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/33820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Gerrit-Change-Number: 33820 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add INVERT to all IOAPIC pads
by Shelley Chen (Code Review) 02 Jul '19

02 Jul '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33819 Change subject: mb/google/hatch: Add INVERT to all IOAPIC pads ...................................................................... mb/google/hatch: Add INVERT to all IOAPIC pads Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by slicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c 2 files changed, 12 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33819/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 9529cc7..a4fb4c9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -52,8 +52,8 @@ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* A20 : M2_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A20 : WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), /* * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration @@ -62,11 +62,8 @@ PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), - /* A23 : FPMCU_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -143,11 +140,8 @@ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : GPP_C12 ==> NC */ PAD_NC(GPP_C12, NONE), - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, NONE), + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), /* C15 : WWAN_DPR_SAR_ODL @@ -166,12 +160,8 @@ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ @@ -451,12 +441,8 @@ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 7e73724..f95e022 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,11 +19,8 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; const struct pad_config *override_gpio_table(size_t *num) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Gerrit-Change-Number: 33819 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd: Add picasso to Kconfig
by Marshall Dawson (Code Review) 02 Jul '19

02 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33750 Change subject: soc/amd: Add picasso to Kconfig ...................................................................... soc/amd: Add picasso to Kconfig Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33750/1 diff --git a/src/soc/amd/Kconfig b/src/soc/amd/Kconfig index 0c33b54..7c08f03 100644 --- a/src/soc/amd/Kconfig +++ b/src/soc/amd/Kconfig @@ -1,4 +1,5 @@ # Load all chipsets before common +source "src/soc/amd/picasso/Kconfig" source "src/soc/amd/stoneyridge/Kconfig" # Load common defaults last -- To view, visit https://review.coreboot.org/c/coreboot/+/33750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Gerrit-Change-Number: 33750 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Stub out bootblock
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32413 Change subject: soc/amd/picasso: Stub out bootblock ...................................................................... soc/amd/picasso: Stub out bootblock Because memory is already initialized when the X86 comes out of reset, we don't need the bootblock. The plan is to jump directly to Romstage. The bootblock may be used to initialize hardware blocks beeded for verstage, but in that case, it will run on the PSP, not on the X86. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 1 insertion(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32413/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 9239030..62e4e15 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. - * Copyright (C) 2017 Advanced Micro Devices - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,109 +11,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <assert.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> -#include <smp/node.h> #include <bootblock_common.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> -#include <soc/pci_devs.h> -#include <soc/cpu.h> -#include <soc/northbridge.h> -#include <soc/southbridge.h> -#include <amdblocks/psp.h> -#include <timestamp.h> -#include <halt.h> - -#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" -#endif -#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" -#endif - -/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ -static void amd_initmmio(void) -{ - msr_t mmconf; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int mtrr; - - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - - /* - * todo: AGESA currently writes variable MTRRs. Once that is - * corrected, un-hardcode this MTRR. - * - * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs - * where all cores execute the path. Both cores within a compute - * unit share MTRRs. Programming core0 has the appearance of - * modifying core1 too. Using the pair again will create - * duplicate copies. - */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; - set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); -} asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - amd_initmmio(); - /* - * Call lib/bootblock.c main with BSP, shortcut for APs - */ - if (!boot_cpu()) { - void (*ap_romstage_entry)(void) = - (void (*)(void))get_ap_entry_ptr(); - - ap_romstage_entry(); /* execution does not return */ - halt(); - } - - /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_timestamp(timestamp_get(), NULL, 0); -} - -void bootblock_soc_early_init(void) -{ - /* - * This call (sb_reset_i2c_slaves) was originally early at - * bootblock_c_entry, but had to be moved here. There was an - * unexplained delay in the middle of the i2c transaction when - * we had it in bootblock_c_entry. Moving it to this point - * (or adding delays) fixes the issue. It seems like the processor - * just pauses but we don't know why. - */ - sb_reset_i2c_slaves(); - bootblock_fch_early_init(); - post_code(0x90); -} - -void bootblock_soc_init(void) -{ - if (CONFIG(STONEYRIDGE_UART)) - assert(CONFIG_UART_FOR_CONSOLE >= 0 - && CONFIG_UART_FOR_CONSOLE <= 1); - - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - - bootblock_fch_init(); - - /* Initialize any early i2c buses. */ - i2c_soc_early_init(); + /* This function is here for building/linking only */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/32413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Gerrit-Change-Number: 32413 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Rename makefile.inc back to Makefile.inc
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32411 Change subject: soc/amd/picasso: Rename makefile.inc back to Makefile.inc ...................................................................... soc/amd/picasso: Rename makefile.inc back to Makefile.inc Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I18ee48865fb64265f38179560265827783d50820 --- R src/soc/amd/picasso/Makefile.inc 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32411/1 diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/Makefile.inc similarity index 100% rename from src/soc/amd/picasso/makefile.inc rename to src/soc/amd/picasso/Makefile.inc -- To view, visit https://review.coreboot.org/c/coreboot/+/32411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18ee48865fb64265f38179560265827783d50820 Gerrit-Change-Number: 32411 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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