coreboot-gerrit June 2019

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Change in ...coreboot[master]: payloads/libpayload: Update a Makefile and a wrappter of a compiler i...
by Asami Doi (Code Review) 01 Jul '19

01 Jul '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33287 Change subject: payloads/libpayload: Update a Makefile and a wrappter of a compiler in libpayload in order to build sample payload for QEMU/ARM. ...................................................................... payloads/libpayload: Update a Makefile and a wrappter of a compiler in libpayload in order to build sample payload for QEMU/ARM. Change-Id: Ia32872c43a99357aa966de3582f6fdb2e2652517 Signed-off-by: Asami Doi <doiasami1219(a)gmail.com> --- M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.emulation-qemu-arm M payloads/libpayload/drivers/Makefile.inc M payloads/libpayload/include/arm/arch/io.h M payloads/libpayload/sample/Makefile 5 files changed, 25 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33287/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342..b636080 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -200,5 +200,5 @@ # header to be placed below 0x2000 in the resulting image. See: # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format… - $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC + $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC -lc fi diff --git a/payloads/libpayload/configs/config.emulation-qemu-arm b/payloads/libpayload/configs/config.emulation-qemu-arm new file mode 100644 index 0000000..e498126 --- /dev/null +++ b/payloads/libpayload/configs/config.emulation-qemu-arm @@ -0,0 +1,10 @@ +CONFIG_LP_ARCH_ARM=y +CONFIG_LP_STACK_SIZE=64000 +CONFIG_LP_BASE_ADDRESS=0x62030000 +CONFIG_LP_TINYCURSES=y +CONFIG_LP_8250_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y + diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e7594..7c555fd 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -50,9 +50,7 @@ libc-$(CONFIG_LP_NVRAM) += options.c # Timer drivers -ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0) libc-y += timer/generic.c -endif libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 2743852..58b8a22 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,6 +34,14 @@ #include <stdint.h> #include <arch/cache.h> +#define inb(a) read8((const void *) (a)) +#define inw(a) read16((const void *) (a)) +#define inl(a) read32((const void *) (a)) + +#define outb(v, a) write8((void *) (&v), a) +#define outw(v, a) write16((void *) (&v), a) +#define outl(v, a) write32((void *) (&v), a) + /* * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 * instead for future development. diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index 5931d5e..18121df 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -28,19 +28,20 @@ ## # Sample libpayload Makefile. -include ../.xcompile include ../.config +include ../.xcompile -ARCH-$(CONFIG_LP_ARCH_ARMV) := arm -ARCH-$(CONFIG_LP_ARCH_POWERPC) := powerpc -ARCH-$(CONFIG_LP_ARCH_X86) := i386 +ARCH-$(CONFIG_LP_ARCH_ARM) := arm +ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 +ARCH-$(CONFIG_LP_ARCH_MIPS) := mips CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LIBPAYLOAD_DIR := ../install/libpayload XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas -CFLAGS := -Wall -Werror -Os +CFLAGS := -fno-builtin -Wall -Werror -Os TARGET := hello OBJS := $(TARGET).o -- To view, visit https://review.coreboot.org/c/coreboot/+/33287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia32872c43a99357aa966de3582f6fdb2e2652517 Gerrit-Change-Number: 33287 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHz
by Kyösti Mälkki (Code Review) 01 Jul '19

01 Jul '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33822 ) Change subject: intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHz ...................................................................... Patch Set 2: Gerrit wanted to reflag this as WIP.. -- To view, visit https://review.coreboot.org/c/coreboot/+/33822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Gerrit-Change-Number: 33822 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 30 Jun 2019 22:07:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: pci_ids.h: Add AMD Picasso IDs
by Martin Roth (Code Review) 30 Jun '19

30 Jun '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33748 ) Change subject: pci_ids.h: Add AMD Picasso IDs ...................................................................... pci_ids.h: Add AMD Picasso IDs Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33748 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/include/device/pci_ids.h 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 2c8fadc..35c457a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -304,6 +304,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 +#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 @@ -451,6 +452,12 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e +#define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de +#define PCI_DEVICE_ID_AMD_PCO_HDA1 0x15e3 +#define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 +#define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 + #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 #define PCI_DEVICE_ID_VLSI_82C593 0x0006 -- To view, visit https://review.coreboot.org/c/coreboot/+/33748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3 Gerrit-Change-Number: 33748 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: device/pci_rom: Fix redundant pci_rom_probe() calls
by Mike Banon (Code Review) 30 Jun '19

30 Jun '19

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33909 ) Change subject: device/pci_rom: Fix redundant pci_rom_probe() calls ...................................................................... Patch Set 1: Code-Review+2 Also a nice improvement, and does not cause any issues while being used with CB:31448 / CB:31450 "G505S dGPU support" patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/33909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Gerrit-Change-Number: 33909 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jun 2019 18:13:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_rom: Fix on-board optionrom address
by Mike Banon (Code Review) 30 Jun '19

30 Jun '19

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33908 ) Change subject: device/pci_rom: Fix on-board optionrom address ...................................................................... Patch Set 1: Code-Review+2 Nice improvement, and does not cause any issues while being used with CB:31448 / CB:31450 "G505S dGPU support" patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/33908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Gerrit-Change-Number: 33908 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jun 2019 18:13:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Add commonlib/helpers.h
by HAOUAS Elyes (Code Review) 30 Jun '19

30 Jun '19

HAOUAS Elyes has removed a vote on this change. Change subject: util/sconfig: Add commonlib/helpers.h ...................................................................... Removed Code-Review+2 by HAOUAS Elyes <ehaouas(a)noos.fr> -- To view, visit https://review.coreboot.org/c/coreboot/+/31932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19 Gerrit-Change-Number: 31932 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: deleteVote

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Change in ...coreboot[master]: drivers/intel/wifi: Select DRIVERS_INTEL_WIFI if your mainboard needs it
by HAOUAS Elyes (Code Review) 30 Jun '19

30 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33827 Change subject: drivers/intel/wifi: Select DRIVERS_INTEL_WIFI if your mainboard needs it ...................................................................... drivers/intel/wifi: Select DRIVERS_INTEL_WIFI if your mainboard needs it Change-Id: Iaaab6df43968abada6397acf7402264dea669c21 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/wifi/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33827/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..a597d40 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,10 +1,9 @@ config DRIVERS_INTEL_WIFI - bool "Support Intel PCI-e WiFi adapters" + bool "Intel WiFi" depends on ARCH_X86 - default y if PCIEXP_PLUGIN_SUPPORT + default n help - When enabled, add identifiers in ACPI and SMBIOS tables to - make OS drivers work with certain Intel PCI-e WiFi chipsets. + Enabled, if the mainboard needs Intel WiFi driver. config USE_SAR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/33827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaab6df43968abada6397acf7402264dea669c21 Gerrit-Change-Number: 33827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]superio/smsc: add SCH5636 Super I/O
by Eloy (Code Review) 30 Jun '19

30 Jun '19

Eloy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33912 Change subject: [WIP]superio/smsc: add SCH5636 Super I/O ...................................................................... [WIP]superio/smsc: add SCH5636 Super I/O add LDNs from the datasheet. Power control is being done by the EC which is in the same package. Change-Id: I83548a325bf7d05f96731c3a2e5a5cb7f2780d36 Signed-off-by: Eloy Degen <degeneloy(a)gmail.com> --- D src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl A src/superio/smsc/sch5636/Kconfig A src/superio/smsc/sch5636/Makefile.inc A src/superio/smsc/sch5636/early_serial.c A src/superio/smsc/sch5636/sch5636.h A src/superio/smsc/sch5636/sch5636_early_init.c A src/superio/smsc/sch5636/superio.c 7 files changed, 262 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33912/1 diff --git a/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl b/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl deleted file mode 100644 index 7e55c02..0000000 --- a/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Eloy Degen. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <superio/smsc/sch5147/acpi/superio.asl> diff --git a/src/superio/smsc/sch5636/Kconfig b/src/superio/smsc/sch5636/Kconfig new file mode 100644 index 0000000..5a9aacc --- /dev/null +++ b/src/superio/smsc/sch5636/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_SMSC_SCH5636 + bool diff --git a/src/superio/smsc/sch5636/Makefile.inc b/src/superio/smsc/sch5636/Makefile.inc new file mode 100644 index 0000000..3a25e37 --- /dev/null +++ b/src/superio/smsc/sch5636/Makefile.inc @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-$(CONFIG_SUPERIO_SMSC_SCH5636) += sch5636_early_init.c +romstage-$(CONFIG_SUPERIO_SMSC_SCH5636) += sch5636_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH5636) += superio.c diff --git a/src/superio/smsc/sch5636/early_serial.c b/src/superio/smsc/sch5636/early_serial.c new file mode 100644 index 0000000..f058564 --- /dev/null +++ b/src/superio/smsc/sch5636/early_serial.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pnp_def.h> +#include <stdint.h> + +#include "smscsuperio.h" + +#define SMSC_ENTRY_KEY 0x55 +#define SMSC_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(SMSC_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(SMSC_EXIT_KEY, port); +} + + +/** + * Enable the specified serial port. + * + * @param dev The device to use. + * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). + */ +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch5636/sch5636.h b/src/superio/smsc/sch5636/sch5636.h new file mode 100644 index 0000000..3a83aa2 --- /dev/null +++ b/src/superio/smsc/sch5636/sch5636.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_SCH_5636_H +#define SUPERIO_SCH_5636_H + +/* LDN are listed on page 26 of the datasheet */ + +#define SCH5636_FDD 0x0B /* FDD */ +#define SCH5636_LPT 0x11 /* LPT */ +#define SMSCSUPERIO_SP1 0x07 /* Com1 */ +#define SMSCSUPERIO_SP2 0x08 /* Com2 */ +#define SCH5636_RTC /* RTC is not available */ +#define SCH5636_KBC 1 /* KBC */ +#define SCH5636_HWM /* HWM is done by the EC */ +#define SCH5636_RUNTIME 0x0A /* Runtime */ +#define SCH5636_XBUS 0x0B /* X-BUS */ + +void sch5636_early_init(unsigned int port); + +#endif /* SUPERIO_SCH_5636_H */ diff --git a/src/superio/smsc/sch5636/sch5636_early_init.c b/src/superio/smsc/sch5636/sch5636_early_init.c new file mode 100644 index 0000000..1ac1925 --- /dev/null +++ b/src/superio/smsc/sch5636/sch5636_early_init.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "sch5636.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +void sch5636_early_init(unsigned int port) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config(dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH5636_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch5636/superio.c b/src/superio/smsc/sch5636/superio.c new file mode 100644 index 0000000..d08d62a --- /dev/null +++ b/src/superio/smsc/sch5636/superio.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> +#include <stdlib.h> + +#include "sch5636.h" + +static void sch5636_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case SCH5636_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch5636_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, SCH5636_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x7ff, 0x7ff, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch5636_ops = { + CHIP_NAME("SMSC SCH5636 Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/33912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83548a325bf7d05f96731c3a2e5a5cb7f2780d36 Gerrit-Change-Number: 33912 Gerrit-PatchSet: 1 Gerrit-Owner: Eloy Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: [WIP]superio/smsc: add SCH5636 Super I/O
by Eloy (Code Review) 30 Jun '19

30 Jun '19

Eloy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33911 Change subject: [WIP]superio/smsc: add SCH5636 Super I/O ...................................................................... [WIP]superio/smsc: add SCH5636 Super I/O add LDNs from the datasheet. Power control is being done by the EC which is in the same package. Change-Id: I173b655c1629885057c1522a75585946f99a3dca Signed-off-by: Eloy Degen <degeneloy(a)gmail.com> --- D src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl A src/superio/smsc/sch5636/Kconfig A src/superio/smsc/sch5636/Makefile.inc A src/superio/smsc/sch5636/early_serial.c A src/superio/smsc/sch5636/sch5636.h A src/superio/smsc/sch5636/sch5636_early_init.c A src/superio/smsc/sch5636/superio.c 7 files changed, 262 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33911/1 diff --git a/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl b/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl deleted file mode 100644 index 7e55c02..0000000 --- a/src/mainboard/fujitsu/esprimo_e900/acpi/superio.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Eloy Degen. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <superio/smsc/sch5147/acpi/superio.asl> diff --git a/src/superio/smsc/sch5636/Kconfig b/src/superio/smsc/sch5636/Kconfig new file mode 100644 index 0000000..5a9aacc --- /dev/null +++ b/src/superio/smsc/sch5636/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_SMSC_SCH5636 + bool diff --git a/src/superio/smsc/sch5636/Makefile.inc b/src/superio/smsc/sch5636/Makefile.inc new file mode 100644 index 0000000..3a25e37 --- /dev/null +++ b/src/superio/smsc/sch5636/Makefile.inc @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-$(CONFIG_SUPERIO_SMSC_SCH5636) += sch5636_early_init.c +romstage-$(CONFIG_SUPERIO_SMSC_SCH5636) += sch5636_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH5636) += superio.c diff --git a/src/superio/smsc/sch5636/early_serial.c b/src/superio/smsc/sch5636/early_serial.c new file mode 100644 index 0000000..f058564 --- /dev/null +++ b/src/superio/smsc/sch5636/early_serial.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pnp_def.h> +#include <stdint.h> + +#include "smscsuperio.h" + +#define SMSC_ENTRY_KEY 0x55 +#define SMSC_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(SMSC_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(SMSC_EXIT_KEY, port); +} + + +/** + * Enable the specified serial port. + * + * @param dev The device to use. + * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). + */ +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch5636/sch5636.h b/src/superio/smsc/sch5636/sch5636.h new file mode 100644 index 0000000..3a83aa2 --- /dev/null +++ b/src/superio/smsc/sch5636/sch5636.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_SCH_5636_H +#define SUPERIO_SCH_5636_H + +/* LDN are listed on page 26 of the datasheet */ + +#define SCH5636_FDD 0x0B /* FDD */ +#define SCH5636_LPT 0x11 /* LPT */ +#define SMSCSUPERIO_SP1 0x07 /* Com1 */ +#define SMSCSUPERIO_SP2 0x08 /* Com2 */ +#define SCH5636_RTC /* RTC is not available */ +#define SCH5636_KBC 1 /* KBC */ +#define SCH5636_HWM /* HWM is done by the EC */ +#define SCH5636_RUNTIME 0x0A /* Runtime */ +#define SCH5636_XBUS 0x0B /* X-BUS */ + +void sch5636_early_init(unsigned int port); + +#endif /* SUPERIO_SCH_5636_H */ diff --git a/src/superio/smsc/sch5636/sch5636_early_init.c b/src/superio/smsc/sch5636/sch5636_early_init.c new file mode 100644 index 0000000..1ac1925 --- /dev/null +++ b/src/superio/smsc/sch5636/sch5636_early_init.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "sch5636.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +void sch5636_early_init(unsigned int port) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config(dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH5636_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch5636/superio.c b/src/superio/smsc/sch5636/superio.c new file mode 100644 index 0000000..d08d62a --- /dev/null +++ b/src/superio/smsc/sch5636/superio.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> +#include <stdlib.h> + +#include "sch5636.h" + +static void sch5636_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case SCH5636_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch5636_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, SCH5636_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x7ff, 0x7ff, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch5636_ops = { + CHIP_NAME("SMSC SCH5636 Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/33911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I173b655c1629885057c1522a75585946f99a3dca Gerrit-Change-Number: 33911 Gerrit-PatchSet: 1 Gerrit-Owner: Eloy Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [WIP] add i945G based mainboard
by HAOUAS Elyes (Code Review) 30 Jun '19

30 Jun '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25509 ) Change subject: [WIP] add i945G based mainboard ...................................................................... Patch Set 28: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 28 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jun 2019 10:29:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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