coreboot-gerrit June 2019

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Change in ...coreboot[master]: soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32410 Change subject: soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO ...................................................................... soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/makefile.inc 2 files changed, 6 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32410/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 29ab149..feaabac 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -13,17 +13,12 @@ ## GNU General Public License for more details. ## -config SOC_AMD_STONEYRIDGE_FP4 +config SOC_AMD_PICASSO bool help - AMD Stoney Ridge FP4 support + AMD Picasso support -config SOC_AMD_STONEYRIDGE_FT4 - bool - help - AMD Stoney Ridge FT4 support - -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +if SOC_AMD_PICASSO config CPU_SPECIFIC_OPTIONS def_bool y @@ -379,4 +374,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index cc8be37..470960b 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -314,4 +314,4 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/32410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 Gerrit-Change-Number: 32410 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Change header guards from stoney to picasso
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32409 Change subject: soc/amd/picasso: Change header guards from stoney to picasso ...................................................................... soc/amd/picasso: Change header guards from stoney to picasso TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 --- M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/include/soc/smbus.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/southbridge.h 11 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32409/1 diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 15a41ed..71fe10e 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef __SOC_PICASSO_ACPI_H__ +#define __SOC_PICASSO_ACPI_H__ #include <arch/acpi.h> @@ -37,4 +37,4 @@ const char *soc_acpi_name(const struct device *dev); -#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 934a9f2..d9d48ad 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef __PICASSO_CPU_H__ +#define __PICASSO_CPU_H__ #include <device/device.h> @@ -32,4 +32,4 @@ void stoney_init_cpus(struct device *dev); void check_mca(void); -#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index fe8240f..94d3eef 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef __PICASSO_GPIO_H__ +#define __PICASSO_GPIO_H__ #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -605,4 +605,4 @@ int gpio_interrupt_status(gpio_t gpio); #endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* __PICASSO_GPIO_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 613dd04..277a8fb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef __SOC_PICASSO_IOMAP_H__ +#define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -79,4 +79,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* __SOC_PICASSO_IOMAP_H__ */ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 563dae0..8405e9c 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef __PI_PICASSO_NORTHBRIDGE_H__ +#define __PI_PICASSO_NORTHBRIDGE_H__ #include <device/device.h> @@ -129,4 +129,4 @@ void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 08d4697..8ce5da6 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -21,8 +21,8 @@ * */ -#ifndef __SOC_STONEYRIDGE_NVS_H__ -#define __SOC_STONEYRIDGE_NVS_H__ +#ifndef __SOC_PICASSO_NVS_H__ +#define __SOC_PICASSO_NVS_H__ #include <commonlib/helpers.h> #include <stdint.h> @@ -64,4 +64,4 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_STONEYRIDGE_NVS_H__ */ +#endif /* __SOC_PICASSO_NVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 02fed7a..478a2cb 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef __PI_PICASSO_PCI_DEVS_H__ +#define __PI_PICASSO_PCI_DEVS_H__ #include <device/pci_def.h> @@ -195,4 +195,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* __PI_PICASSO_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index 6ce79b4..d8b2900 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef __PICASSO_ROMSTAGE_H__ +#define __PICASSO_ROMSTAGE_H__ void mainboard_romstage_entry(int s3_resume); -#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h index 71f7faf..7b05610 100644 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_SMBUS_H__ -#define __STONEYRIDGE_SMBUS_H__ +#ifndef __PICASSO_SMBUS_H__ +#define __PICASSO_SMBUS_H__ #include <stdint.h> #include <soc/iomap.h> @@ -55,4 +55,4 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* __STONEYRIDGE_SMBUS_H__ */ +#endif /* __PICASSO_SMBUS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index d22b8db..46c4a8c 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ #define SMI_GEVENTS 24 @@ -238,4 +238,4 @@ void enable_smi_generation(void); #endif -#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 9fa93c8..a6d144a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef __PICASSO_SB_H__ +#define __PICASSO_SB_H__ #include <types.h> #include <device/device.h> @@ -609,4 +609,4 @@ */ void set_pm1cnt_s5(void); -#endif /* __STONEYRIDGE_H__ */ +#endif /* __PICASSO_SB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Gerrit-Change-Number: 32409 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Remove files we're not using
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32408 Change subject: soc/amd/picasso: Remove files we're not using ...................................................................... soc/amd/picasso: Remove files we're not using Remove files that aren't needed for the picasso port. Picasso (and all AMD Zen processors) have a very different boot flow than the previous processors. The memory is initialized by the PSP before the X86 processor is released from reset. The SPD is read by the PSP, so it's not needed in coreboot. I discussed with AMD whether we could continue to let coreboot do the memory initialization instead of the PSP, but the ability to do Cache-as-RAM has been removed, so while it might be possible, it would have to be all written in ASM. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 --- D src/soc/amd/picasso/BiosCallOuts.c D src/soc/amd/picasso/enable_usbdebug.c M src/soc/amd/picasso/makefile.inc D src/soc/amd/picasso/nb_util.c D src/soc/amd/picasso/smbus_spd.c 5 files changed, 0 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32408/1 diff --git a/src/soc/amd/picasso/BiosCallOuts.c b/src/soc/amd/picasso/BiosCallOuts.c deleted file mode 100644 index 1027ae0..0000000 --- a/src/soc/amd/picasso/BiosCallOuts.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <amdblocks/BiosCallOuts.h> -#include <soc/southbridge.h> -#include <soc/pci_devs.h> -#include <stdlib.h> - -#include <amdblocks/agesawrapper.h> -#include <amdblocks/dimm_spd.h> -#include "chip.h" -#include <amdblocks/car.h> - -void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} - -AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset; - FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - /* Get platform specific configuration changes */ - platform_FchParams_reset(FchParams_reset); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - - if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* XHCI configuration */ - if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) - FchParams_env->Usb.Xhci0Enable = TRUE; - else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; - - /* SATA configuration */ - FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } - } else - FchParams_env->Sata.SataIdeMode = FALSE; - - /* Platform updates */ - platform_FchParams_env(FchParams_env); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - uint8_t spd_address; - int err; - DEVTREE_CONST struct device *dev; - DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - dev = pcidev_path_on_root(DCT_DEVFN); - if (dev == NULL) - return AGESA_ERROR; - - conf = dev->chip_info; - if (conf == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0])) - return AGESA_ERROR; - - spd_address = conf->spd_addr_lookup - [info->SocketId][info->MemChannelId][info->DimmId]; - if (spd_address == 0) - return AGESA_ERROR; - - err = mainboard_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - /* Read the SPD if the mainboard didn't fill the buffer */ - if (err || (*info->Buffer == 0)) - err = sb_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - if (err) - return AGESA_ERROR; - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; - uint32_t flags = 0; - - if (info->PrimaryCore == TRUE) - return AGESA_UNSUPPORTED; /* force normal path */ - if (info->ExecWbinvd == TRUE) - flags |= 1; - if (info->CacheEn == TRUE) - flags |= 2; - - ap_teardown_car(flags); /* does not return */ - - /* Should never reach here */ - return AGESA_UNSUPPORTED; -} - -/* Allow mainboards to fill the SPD buffer */ -__weak int mainboard_read_spd(uint8_t spdAddress, char *buf, - size_t len) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - return -1; /* SPD not read */ -} diff --git a/src/soc/amd/picasso/enable_usbdebug.c b/src/soc/amd/picasso/enable_usbdebug.c deleted file mode 100644 index ce84a47..0000000 --- a/src/soc/amd/picasso/enable_usbdebug.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - /* Enable all of the USB controllers */ - outb(PM_USB_ENABLE, PM_INDEX); - outb(PM_USB_ALL_CONTROLLERS, PM_DATA); - - return SOC_EHCI1_DEV; -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 reg32, value; - - value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT; - value |= DEBUG_PORT_ENABLE; - reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); - reg32 &= ~DEBUG_PORT_MASK; - reg32 |= value; - pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); -} diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index 68dba09..cc8be37 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -38,7 +38,6 @@ subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c -bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c @@ -53,7 +52,6 @@ bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c @@ -68,7 +66,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -80,7 +77,6 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c @@ -91,12 +87,10 @@ postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c -ramstage-y += BiosCallOuts.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += mca.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += hda.c @@ -119,7 +113,6 @@ ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c -ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c @@ -128,7 +121,6 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c -smm-y += nb_util.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/picasso/nb_util.c b/src/soc/amd/picasso/nb_util.c deleted file mode 100644 index d5de067..0000000 --- a/src/soc/amd/picasso/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/northbridge.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/picasso/smbus_spd.c b/src/soc/amd/picasso/smbus_spd.c deleted file mode 100644 index 63b457c..0000000 --- a/src/soc/amd/picasso/smbus_spd.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/agesawrapper.h> -#include <device/pci_def.h> -#include <device/device.h> -#include <soc/southbridge.h> -#include <soc/smbus.h> -#include <amdblocks/dimm_spd.h> - -/* - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ -static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) -{ - uint8_t dev_addr; - size_t index; - int error; - char *pbuf = buffer; - - printk(BIOS_SPEW, "-------------READING SPD-----------\n"); - printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n", - SmbusSlaveAddress, count); - - /* - * Convert received device address to the format accepted by - * do_smbus_read_byte and do_smbus_recv_byte. - */ - dev_addr = (SmbusSlaveAddress >> 1); - - /* Read the first SPD byte */ - error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - - /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ - for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - } - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n"); - - return 0; -} - -int sb_read_spd(uint8_t spdAddress, char *buf, size_t len) -{ - return readspd(spdAddress, buf, len); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/32408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 Gerrit-Change-Number: 32408 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: soc/amd/picasso: Create picasso as a copy of stoneyridge
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32407 Change subject: soc/amd/picasso: Create picasso as a copy of stoneyridge ...................................................................... soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe it's the most transparent Makefile.inc has been renamed as makefile.inc until it's updated. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b --- A src/soc/amd/picasso/BiosCallOuts.c A src/soc/amd/picasso/Kconfig A src/soc/amd/picasso/acpi.c A src/soc/amd/picasso/acpi/acpi_wake_source.asl A src/soc/amd/picasso/acpi/cpu.asl A src/soc/amd/picasso/acpi/globalnvs.asl A src/soc/amd/picasso/acpi/gpio_lib.asl A src/soc/amd/picasso/acpi/lpc.asl A src/soc/amd/picasso/acpi/northbridge.asl A src/soc/amd/picasso/acpi/pci_int.asl A src/soc/amd/picasso/acpi/pcie.asl A src/soc/amd/picasso/acpi/sb_fch.asl A src/soc/amd/picasso/acpi/sb_pci0_fch.asl A src/soc/amd/picasso/acpi/sleepstates.asl A src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/acpi/usb.asl A src/soc/amd/picasso/bootblock/bootblock.c A src/soc/amd/picasso/chip.c A src/soc/amd/picasso/chip.h A src/soc/amd/picasso/cpu.c A src/soc/amd/picasso/enable_usbdebug.c A src/soc/amd/picasso/finalize.c A src/soc/amd/picasso/gpio.c A src/soc/amd/picasso/hda.c A src/soc/amd/picasso/i2c.c A src/soc/amd/picasso/include/soc/acpi.h A src/soc/amd/picasso/include/soc/amd_pci_int_defs.h A src/soc/amd/picasso/include/soc/cpu.h A src/soc/amd/picasso/include/soc/gpio.h A src/soc/amd/picasso/include/soc/iomap.h A src/soc/amd/picasso/include/soc/northbridge.h A src/soc/amd/picasso/include/soc/nvs.h A src/soc/amd/picasso/include/soc/pci_devs.h A src/soc/amd/picasso/include/soc/romstage.h A src/soc/amd/picasso/include/soc/smbus.h A src/soc/amd/picasso/include/soc/smi.h A src/soc/amd/picasso/include/soc/southbridge.h A src/soc/amd/picasso/iommu.c A src/soc/amd/picasso/lpc.c A src/soc/amd/picasso/makefile.inc A src/soc/amd/picasso/mca.c A src/soc/amd/picasso/monotonic_timer.c A src/soc/amd/picasso/nb_util.c A src/soc/amd/picasso/northbridge.c A src/soc/amd/picasso/pmutil.c A src/soc/amd/picasso/ramtop.c A src/soc/amd/picasso/reset.c A src/soc/amd/picasso/romstage.c A src/soc/amd/picasso/sata.c A src/soc/amd/picasso/sb_util.c A src/soc/amd/picasso/sm.c A src/soc/amd/picasso/smbus.c A src/soc/amd/picasso/smbus_spd.c A src/soc/amd/picasso/smi.c A src/soc/amd/picasso/smi_util.c A src/soc/amd/picasso/smihandler.c A src/soc/amd/picasso/southbridge.c A src/soc/amd/picasso/spi.c A src/soc/amd/picasso/tsc_freq.c A src/soc/amd/picasso/uart.c A src/soc/amd/picasso/usb.c 61 files changed, 11,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32407/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Gerrit-Change-Number: 32407 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

10 37

Change in ...coreboot[master]: mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ density
by Kevin Chiu (Code Review) 02 Jul '19

02 Jul '19

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33795 Change subject: mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ density ...................................................................... mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ density Samsung K4F6E3S4HM-MGCJ density is 16Gb BUG=b:121228792 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage MemTotal: 8041964kB in /proc/meminfo Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/reef/variants/baseboard/memory.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/33795/1 diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index f298cae..7673107 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -140,8 +140,8 @@ /* K4F6E3S4HM-MGCJ - both logical channels */ [7] = { .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_16Gb_DENSITY, + .ch1_rank_density = LP4_16Gb_DENSITY, .part_num = "K4F6E3S4HM-MGCJ", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Gerrit-Change-Number: 33795 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: util/superiotool/nuvoton.c: Minor tag update/removal
by Pavel Sayekat (Code Review) 02 Jul '19

02 Jul '19

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33910 Change subject: util/superiotool/nuvoton.c: Minor tag update/removal ...................................................................... util/superiotool/nuvoton.c: Minor tag update/removal Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6 --- M util/superiotool/nuvoton.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33910/1 diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7552244..81bff96 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -594,7 +594,7 @@ {0x05, "Keyboard Controller", {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, - {0x06, "CIR", + {0x06, "Consumer IR", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, {0x07, "GPIO 7, GPIO 8", @@ -622,7 +622,7 @@ {0x00,0x00,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x7f,0xa8, 0x08,0x7f,0x00,0x81,0x00,0x00,0x00,0x00,0x87,0x47, 0x00,0x00,0x00,0x02,EOT}}, - {0x0d, "BCLK, WDT2", + {0x0d, "WDT2", {0xe7,0xe8,0xeb,0xed,0xf0,0xf3,EOT}, {0x10,0x32,0x14,0x00,0x00,0x00,EOT}}, {0x0e, "CIR Wake-Up", -- To view, visit https://review.coreboot.org/c/coreboot/+/33910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6 Gerrit-Change-Number: 33910 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: QC common: fix compiler complaint, missing <string.h>
by mturney mturney (Code Review) 02 Jul '19

02 Jul '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33445 Change subject: QC common: fix compiler complaint, missing <string.h> ...................................................................... QC common: fix compiler complaint, missing <string.h> Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/common/qclib.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33445/1 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 73c5250..5df5b52 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -16,6 +16,7 @@ #include <console/cbmem_console.h> #include <cbmem.h> #include <boardid.h> +#include <string.h> #include <fmap.h> #include <assert.h> #include <arch/mmu.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715 Gerrit-Change-Number: 33445 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: string.h: Move common string functions into .c file
by Julius Werner (Code Review) 02 Jul '19

02 Jul '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32901 Change subject: string.h: Move common string functions into .c file ...................................................................... string.h: Move common string functions into .c file There's no clear reason why most of coreboot's basic string functions are static inline. These functions don't particularly benefit from inlining (at least not notably more than other functions). This patch moves them to string.c to be more consistent with our usual coding practices. Leaving the ctype functions as static inline because they actually seem small and collapsable enough that inlining seems reasonable. Also clarified the situation of strdup() and strconcat() a bit more and optimized strrchr() to be single-pass. Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/string.h M src/lib/Makefile.inc M src/lib/string.c 3 files changed, 127 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32901/1 diff --git a/src/include/string.h b/src/include/string.h index 65ce561..278d7c6 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -25,33 +25,13 @@ #endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); - -// simple string functions - -static inline size_t strnlen(const char *src, size_t max) -{ - size_t i = 0; - while ((*src++) && (i < max)) - i++; - return i; -} - -static inline size_t strlen(const char *src) -{ - size_t i = 0; - while (*src++) - i++; - return i; -} - -static inline char *strchr(const char *s, int c) -{ - for (; *s; s++) { - if (*s == c) - return (char *) s; - } - return 0; -} +size_t strnlen(const char *src, size_t max); +size_t strlen(const char *src); +char *strchr(const char *s, int c); +char *strncpy(char *to, const char *from, int count); +char *strcpy(char *dst, const char *src); +int strcmp(const char *s1, const char *s2); +int strncmp(const char *s1, const char *s2, int maxlen); /** * Find a character in a string. @@ -61,71 +41,12 @@ * @return A pointer to the last occurrence of the character in the * string, or NULL if the character was not encountered within the string. */ -static inline char *strrchr(const char *s, int c) -{ - char *p = (char *)s + strlen(s); +char *strrchr(const char *s, int c); - for (; p >= s; p--) { - if (*p == c) - return p; - } - - return NULL; -} - -static inline char *strncpy(char *to, const char *from, int count) -{ - register char *ret = to; - register char data; - - while (count > 0) { - count--; - data = *from++; - *to++ = data; - if (data == '\0') - break; - } - - while (count > 0) { - count--; - *to++ = '\0'; - } - return ret; -} - -static inline char *strcpy(char *dst, const char *src) -{ - char *ptr = dst; - - while (*src) - *dst++ = *src++; - *dst = '\0'; - - return ptr; -} - -static inline int strcmp(const char *s1, const char *s2) -{ - int r; - - while ((r = (*s1 - *s2)) == 0 && *s1) { - s1++; - s2++; - } - return r; -} - -static inline int strncmp(const char *s1, const char *s2, int maxlen) -{ - int i; - - for (i = 0; i < maxlen; i++) { - if ((s1[i] != s2[i]) || (s1[i] == '\0')) - return s1[i] - s2[i]; - } - - return 0; -} +/* Parses an unsigned integer and moves the input pointer forward to the first + character that's not a valid digit. s and *s must not be NULL. Result + undefined if it overruns the return type size. */ +unsigned int skip_atoi(char **s); static inline int isspace(int c) { @@ -179,16 +100,4 @@ return c; } -/* Parses an unsigned integer and moves the input pointer forward to the first - character that's not a valid digit. s and *s must not be NULL. Result - undefined if it overruns the return type size. */ -static inline unsigned int skip_atoi(char **s) -{ - unsigned int i = 0; - - while (isdigit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - #endif /* STRING_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..913675b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -118,7 +118,6 @@ ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c -ramstage-y += string.c ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c @@ -244,6 +243,14 @@ ramstage-y += reset.c smm-y += reset.c +decompressor-y += string.c +bootblock-y += string.c +verstage-y += string.c +romstage-y += string.c +postcar-y += string.c +ramstage-y += string.c +smm-y += string.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/string.c b/src/lib/string.c index 2e71489f..f8ec9de 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -1,9 +1,14 @@ +#include <assert.h> +#include <rules.h> #include <string.h> #include <stddef.h> #include <stdlib.h> char *strdup(const char *s) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz = strlen(s) + 1; char *d = malloc(sz); if (d) @@ -13,6 +18,9 @@ char *strconcat(const char *s1, const char *s2) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz_1 = strlen(s1); size_t sz_2 = strlen(s2); char *d = malloc(sz_1 + sz_2 + 1); @@ -22,3 +30,102 @@ } return d; } + +size_t strnlen(const char *src, size_t max) +{ + size_t i = 0; + while ((*src++) && (i < max)) + i++; + return i; +} + +size_t strlen(const char *src) +{ + size_t i = 0; + while (*src++) + i++; + return i; +} + +char *strchr(const char *s, int c) +{ + for (; *s; s++) { + if (*s == c) + return (char *)s; + } + return NULL; +} + +char *strrchr(const char *s, int c) +{ + char *p = NULL; + + for (; *s; s++) + if (*s == c) + p = (char *)s; + + return p; +} + +char *strncpy(char *to, const char *from, int count) +{ + register char *ret = to; + register char data; + + while (count > 0) { + count--; + data = *from++; + *to++ = data; + if (data == '\0') + break; + } + + while (count > 0) { + count--; + *to++ = '\0'; + } + return ret; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while (*src) + *dst++ = *src++; + *dst = '\0'; + + return ptr; +} + +int strcmp(const char *s1, const char *s2) +{ + int r; + + while ((r = (*s1 - *s2)) == 0 && *s1) { + s1++; + s2++; + } + return r; +} + +int strncmp(const char *s1, const char *s2, int maxlen) +{ + int i; + + for (i = 0; i < maxlen; i++) { + if ((s1[i] != s2[i]) || (s1[i] == '\0')) + return s1[i] - s2[i]; + } + + return 0; +} + +unsigned int skip_atoi(char **s) +{ + unsigned int i = 0; + + while (isdigit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36 Gerrit-Change-Number: 32901 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/lib: Add option to support native display init with vboot 2.0
by Amol N Sukerkar (Code Review) 01 Jul '19

01 Jul '19

Amol N Sukerkar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33845 Change subject: src/lib: Add option to support native display init with vboot 2.0 ...................................................................... src/lib: Add option to support native display init with vboot 2.0 This change allows display initialization natively in coreboot with vboot 2.0 authentication mechanism is enabled on a non-chromeos platform. TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display should initialize in ramstage when platform boots. Set CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display initialization should be skipped in coreboot. Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar(a)intel.com> Change-Id: I51361c267e0317d44a58cc5d740c3beb8924a57b --- M src/lib/bootmode.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33845/1 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 737dcf9..bb14cd1 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2019 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,8 +34,12 @@ int display_init_required(void) { - /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ - if (CONFIG(VBOOT)) { + /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. + * VBOOT_MAY_SKIP_DISPLAY_INIT, when selected, assumes + * CHROMEOS configuration and allows the platform to skip + * display init in normal boot. + */ + if (CONFIG(VBOOT_MAY_SKIP_DISPLAY_INIT)) { /* Must always select MUST_REQUEST_DISPLAY when using this function. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) -- To view, visit https://review.coreboot.org/c/coreboot/+/33845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51361c267e0317d44a58cc5d740c3beb8924a57b Gerrit-Change-Number: 33845 Gerrit-PatchSet: 1 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbmem: Update banner string regular expression
by You-Cheng Syu (Code Review) 01 Jul '19

01 Jul '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33779 Change subject: util/cbmem: Update banner string regular expression ...................................................................... util/cbmem: Update banner string regular expression Banner string format has been changed (https://review.coreboot.org/30935). We should update our regular expression correspondingly. Also add "verstage" into the stage search list since some boards (e.g., Kukui) might start console initialization at verstage. Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M util/cbmem/cbmem.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/33779/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 52fdc9b..6f8216a 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -797,9 +797,12 @@ a banner, store the last match for that stage in cursor and stop. */ cursor = 0; if (one_boot_only) { -#define BANNER_REGEX(stage) "\n\ncoreboot-[^\n]* " stage " starting\\.\\.\\.\n" +#define BANNER_REGEX(stage) \ + "\n\ncoreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" #define OVERFLOW_REGEX(stage) "\n\\*\\*\\* Pre-CBMEM " stage " console overflow" const char *regex[] = { BANNER_REGEX("bootblock"), + OVERFLOW_REGEX("verstage"), + BANNER_REGEX("verstage"), OVERFLOW_REGEX("romstage"), BANNER_REGEX("romstage"), OVERFLOW_REGEX("ramstage"), -- To view, visit https://review.coreboot.org/c/coreboot/+/33779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463 Gerrit-Change-Number: 33779 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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