coreboot-gerrit June 2019

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Change in ...coreboot[master]: nb/intel/nehalem: Die if no memory ranks found
by Jacob Garber (Code Review) 10 Jul '19

10 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33403 Change subject: nb/intel/nehalem: Die if no memory ranks found ...................................................................... nb/intel/nehalem: Die if no memory ranks found Die if there are no memory ranks found to prevent a division by zero. Change-Id: I6146dd8420f3734d1a672a9f29a098f47fcb739c Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1229628 --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33403/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 15d6abb..03831e2 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1010,6 +1010,9 @@ } } + if (count == 0) + die("No memory ranks found for channel %u\n", channel); + info->avg4044[channel] = sum / count; info->max4048[channel] = max_of_unk; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6146dd8420f3734d1a672a9f29a098f47fcb739c Gerrit-Change-Number: 33403 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: soc/intel/block/cpu: Make MP init options mutually exclusive
by Arthur Heymans (Code Review) 10 Jul '19

10 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33357 Change subject: soc/intel/block/cpu: Make MP init options mutually exclusive ...................................................................... soc/intel/block/cpu: Make MP init options mutually exclusive It shouldn't be the case that multiple or no MP init paths could be selected. Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 30 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33357/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9ec5307..e602829 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,29 +51,49 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -menu "Multiple Processor (MP) Initialization Options" -config USE_COREBOOT_NATIVE_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT bool "Perform MP Initialization by coreboot" - default y if !PLATFORM_USES_FSP2_1 - default n + select USE_COREBOOT_NATIVE_MP_INIT help This option allows user to select native coreboot option to perform multiprocessor initialization. -config USE_INTEL_FSP_MP_INIT +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT help This option allows FSP to perform multiprocessor initialization. -config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI select USE_COREBOOT_NATIVE_MP_INIT help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -endmenu # Multiple Processor (MP) Initialization Options +endchoice + +config USE_COREBOOT_NATIVE_MP_INIT + bool + help + This option allows user to select native coreboot option to perform + multiprocessor initialization. + +config USE_INTEL_FSP_MP_INIT + bool + help + This option allows FSP to perform multiprocessor initialization. + +config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool + select USE_COREBOOT_NATIVE_MP_INIT + help + This option allows FSP to make use of MP services PPI published by + coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Gerrit-Change-Number: 33357 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 20

Change in ...coreboot[master]: vendorcode/eltan Add hashing library used for measured and verified b...
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30831 Change subject: vendorcode/eltan Add hashing library used for measured and verified boot. ...................................................................... vendorcode/eltan Add hashing library used for measured and verified boot. To avoid having the whole 3rdparty/vboot/firmware included a small hashing library has been created. Create library which is a 'wrapper' using only sha1, sha256 and sha512 of 3rdparty/vboot/firmware. Fucntions cb_sha1(), cb_sha256() and cb_sha512 can be used for hashing. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/vendorcode/eltan/security/include/cb_sha1.h A src/vendorcode/eltan/security/include/cb_sha256.h A src/vendorcode/eltan/security/include/cb_sha512.h A src/vendorcode/eltan/security/include/cryptolib.h A src/vendorcode/eltan/security/lib/Makefile.inc A src/vendorcode/eltan/security/lib/cb_sha1.c A src/vendorcode/eltan/security/lib/cb_sha256.c A src/vendorcode/eltan/security/lib/cb_sha512.c 8 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30831/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha1.h b/src/vendorcode/eltan/security/include/cb_sha1.h new file mode 100644 index 0000000..3b72355 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha1.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA1_H__ +#define __SECURITY_SHA1_H__ + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha256.h b/src/vendorcode/eltan/security/include/cb_sha256.h new file mode 100644 index 0000000..3b45f73 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha256.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA256_H__ +#define __SECURITY_SHA256_H__ + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha512.h b/src/vendorcode/eltan/security/include/cb_sha512.h new file mode 100644 index 0000000..a383cf0 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha512.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA512_H__ +#define __SECURITY_SHA512_H__ + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cryptolib.h b/src/vendorcode/eltan/security/include/cryptolib.h new file mode 100644 index 0000000..ac1668a --- /dev/null +++ b/src/vendorcode/eltan/security/include/cryptolib.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_CRYPTOLIB_H__ +#define __SECURITY_CRYPTOLIB_H__ + +#define NEED_VB2_SHA_LIBRARY + +#include <2rsa.h> +#include <vb21_common.h> +#include <vb2_api.h> + +#include "cb_sha1.h" +#include "cb_sha512.h" +#include "cb_sha256.h" + +#endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc new file mode 100644 index 0000000..9e2fc39 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +SECURITYLIB_INCLUDES = -I3rdparty/vboot/firmware/2lib/include -I3rdparty/vboot/firmware/lib21/include + +CPPFLAGS_common+=$(SECURITYLIB_INCLUDES) + +ifeq ($(CONFIG_VERIFIED_BOOT),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2common.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +ifeq ($(CONFIG_VERIFIED_BOOT_USE_SHA512),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha512.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +else +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha256.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +endif +endif + +ifeq ($(CONFIG_MBOOT),y) +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +ramstage-y += cb_sha1.c +ramstage-y += cb_sha512.c +ramstage-y += cb_sha256.c + +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2common.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +romstage-y += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +romstage-y += cb_sha1.c +romstage-y += cb_sha512.c +romstage-y += cb_sha256.c +endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha1.c b/src/vendorcode/eltan/security/lib/cb_sha1.c new file mode 100644 index 0000000..fd96943 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha1.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + struct vb2_sha1_context ctx; + + vb2_sha1_init(&ctx); + vb2_sha1_update(&ctx, data, len); + vb2_sha1_finalize(&ctx, digest); + + return digest; +} diff --git a/src/vendorcode/eltan/security/lib/cb_sha256.c b/src/vendorcode/eltan/security/lib/cb_sha256.c new file mode 100644 index 0000000..b02ebb2 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha256.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA256_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha256_context ctx; + + vb2_sha256_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha256_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha256_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA256_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA256_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA256 digest */ + return cb_sha256_ex(data, len, digest, 0); +} \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha512.c b/src/vendorcode/eltan/security/lib/cb_sha512.c new file mode 100644 index 0000000..9d713e7 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha512.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA512_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha512_context ctx; + + vb2_sha512_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha512_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha512_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA512_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA512_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA512 digest */ + return cb_sha512_ex(data, len, digest, 0); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Gerrit-Change-Number: 30831 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 18

Change in ...coreboot[master]: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31822 Change subject: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only ...................................................................... soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/acpi/lpc.asl 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31822/1 diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 6b2ecec..a28eb38 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -44,7 +44,10 @@ Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed(ReadOnly, 0xffffffff - + (CONFIG_COREBOOT_ROMSIZE_KB*1024) + 1, + CONFIG_COREBOOT_ROMSIZE_KB*1024) + }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Gerrit-Change-Number: 31822 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
by Bora Guvendik (Code Review) 09 Jul '19

09 Jul '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33818 Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ...................................................................... vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake Update FSP header files with 7.0.64.40 version for Cannonlake platform. Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h 4 files changed, 6,400 insertions(+), 6,381 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Gerrit-Change-Number: 33818 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: src/arch/x86: Prevent attack on null pointer dereference
by John Zhao (Code Review) 08 Jul '19

08 Jul '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33051 Change subject: src/arch/x86: Prevent attack on null pointer dereference ...................................................................... src/arch/x86: Prevent attack on null pointer dereference Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/arch/x86/acpi.c 1 file changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33051/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index d1dcd03..97190d2 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,6 +218,9 @@ memset((void *)madt, 0, sizeof(acpi_madt_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -248,6 +251,9 @@ memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -302,6 +308,9 @@ if (!lasa) return; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TCPA", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -361,6 +370,9 @@ if (!lasa) tpm2_log_len = 0; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -481,6 +493,9 @@ memset((void *)srat, 0, sizeof(acpi_srat_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SRAT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -508,6 +523,9 @@ memset((void *)dmar, 0, sizeof(acpi_dmar_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "DMAR", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -669,6 +687,9 @@ memset((void *)slit, 0, sizeof(acpi_slit_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SLIT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -694,6 +715,9 @@ memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -728,6 +752,9 @@ memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "VFCT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -754,6 +781,9 @@ memset((void *)ivrs, 0, sizeof(acpi_ivrs_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "IVRS", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -807,6 +837,10 @@ current = (uintptr_t)dbg2; memset(dbg2, 0, sizeof(acpi_dbg2_header_t)); header = &(dbg2->header); + + if (!header) + return; + header->revision = get_acpi_table_revision(DBG2); memcpy(header->signature, "DBG2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -926,6 +960,9 @@ { acpi_header_t *header = &(rsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -946,6 +983,9 @@ { acpi_header_t *header = &(xsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -1046,7 +1086,8 @@ memcpy(pos, data, data_len); len += data_len; - header->length += len; + if(header) + header->length += len; return len; } @@ -1058,6 +1099,9 @@ acpi_header_t *header = &(hest->header); memset(hest, 0, sizeof(acpi_hest_t)); + + if (!header) + return; memcpy(header->signature, "HEST", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -1080,6 +1124,9 @@ memset(bert, 0, sizeof(acpi_bert_t)); + if (!header) + return; + memcpy(header->signature, "BERT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1101,6 +1148,10 @@ acpi_header_t *header = &(fadt->header); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + if (!header) + return; + memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); -- To view, visit https://review.coreboot.org/c/coreboot/+/33051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Gerrit-Change-Number: 33051 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33039 Change subject: sb/intel/lynxpoint: Use common final SPI OPs setup ...................................................................... sb/intel/lynxpoint: Use common final SPI OPs setup Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33039/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c1..4efb83e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -960,10 +961,7 @@ static void lpc_final(struct device *dev) { - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; + spi_finalize_ops(); if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); -- To view, visit https://review.coreboot.org/c/coreboot/+/33039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Gerrit-Change-Number: 33039 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: sb/intel/ibexpeak: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33038 Change subject: sb/intel/ibexpeak: Use common final SPI OPs setup ...................................................................... sb/intel/ibexpeak: Use common final SPI OPs setup This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 3 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33038/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index b8129ad..d39a5bd 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -43,34 +43,6 @@ return ARRAY_SIZE(cst_entries); } -static void mainboard_init(struct device *dev) -{ - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); -} - static void fill_ssdt(struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); @@ -80,7 +52,6 @@ { u16 pmbase; - dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 09310ae..6bb546f 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -50,31 +50,6 @@ { u16 pmbase; - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); - int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e7162b1..fa1ca92 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -38,6 +38,7 @@ #include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -785,6 +786,8 @@ static void lpc_final(struct device *dev) { + spi_finalize_ops(); + /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || -- To view, visit https://review.coreboot.org/c/coreboot/+/33038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Gerrit-Change-Number: 33038 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33037 Change subject: sb/intel/i82801gx: Use common final SPI OPs setup ...................................................................... sb/intel/i82801gx: Use common final SPI OPs setup Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33037/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 948b6aa..b226b23 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,6 +33,7 @@ #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/spi.h> #include "i82801gx.h" #include "nvs.h" @@ -620,11 +621,7 @@ if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; - /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); -- To view, visit https://review.coreboot.org/c/coreboot/+/33037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Gerrit-Change-Number: 33037 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: Add a common interface to set final OPs settings
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33036 Change subject: sb/intel/common: Add a common interface to set final OPs settings ...................................................................... sb/intel/common: Add a common interface to set final OPs settings This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu. Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index bf2a44c..0794bb7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -31,6 +31,8 @@ #include <spi-generic.h> +#include "spi.h" + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -1041,6 +1043,45 @@ return 0; } +void spi_finalize_ops(void) +{ + ich_spi_controller *cntlr = &g_cntlr; + u16 spi_opprefix;; + u16 optype = 0; + struct intel_spi_config spi_config = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPTYPE and OPCODE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ + {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ + } + }; + int i; + + if (g_ichspi_lock) + return; + + intel_southbridge_override_spi(&spi_config); + + spi_opprefix = spi_config.opprefixes[0] + | (spi_config.opprefixes[1] << 8); + writew_(spi_opprefix, cntlr->preop); + for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { + optype |= (spi_config.ops[i].type & 3) << (i * 2); + writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + } + writew_(optype, &cntlr->optype); +} + +__weak void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000..fcc5cd8 --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_spi_config *spi_config); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Gerrit-Change-Number: 33036 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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