coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: sb/amd/sr5650: Add fine-grained bounds checking
by Jacob Garber (Code Review) 17 Jul '19

17 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33458 Change subject: sb/amd/sr5650: Add fine-grained bounds checking ...................................................................... sb/amd/sr5650: Add fine-grained bounds checking The code currently checks that 4 <= dev_index <= 10, which after subtraction by 4 can index into an array of length at most 7. This is fine for the largest cpl array (which does have length 7), but is too large for some of the others, which are smaller. This adds bounds checks for each array access to ensure they are all within bounds. Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1229676 --- M src/southbridge/amd/sr5650/pcie.c 1 file changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33458/1 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f87fadb..e90a997 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -360,41 +360,53 @@ static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev) { u8 dev_index; - u8 *slave_cpl; u8 value; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; dev_index = dev->path.pci.devfn >> 3; - if (dev_index < 4 || dev_index > 0xa) { + + if (dev_index < 4) return; - } + + dev_index -= 4; switch (cfg->gpp3a_configuration) { case 0x1: /* 4:2:0:0:0:0 */ - slave_cpl = (u8 *)&pGpp420000; + if (dev_index >= ARRAY_SIZE(pGpp420000)) + return; + value = pGpp420000[dev_index]; break; case 0x2: /* 4:1:1:0:0:0 */ - slave_cpl = (u8 *)&pGpp411000; + if (dev_index >= ARRAY_SIZE(pGpp411000)) + return; + value = pGpp411000[dev_index]; break; case 0xC: /* 2:2:2:0:0:0 */ - slave_cpl = (u8 *)&pGpp222000; + if (dev_index >= ARRAY_SIZE(pGpp222000)) + return; + value = pGpp222000[dev_index]; break; case 0xA: /* 2:2:1:1:0:0 */ - slave_cpl = (u8 *)&pGpp221100; + if (dev_index >= ARRAY_SIZE(pGpp221100)) + return; + value = pGpp221100[dev_index]; break; case 0x4: /* 2:1:1:1:1:0 */ - slave_cpl = (u8 *)&pGpp211110; + if (dev_index >= ARRAY_SIZE(pGpp211110)) + return; + value = pGpp211110[dev_index]; break; case 0xB: /* 1:1:1:1:1:1 */ - slave_cpl = (u8 *)&pGpp111111; + if (dev_index >= ARRAY_SIZE(pGpp111111)) + return; + value = pGpp111111[dev_index]; break; default: /* shouldn't be here. */ printk(BIOS_WARNING, "buggy gpp3a_configuration\n"); return; } - value = slave_cpl[dev_index - 4]; if (value != 0) { set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); -- To view, visit https://review.coreboot.org/c/coreboot/+/33458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b Gerrit-Change-Number: 33458 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: nb/intel/x4x: Die on unknown memory speed
by Jacob Garber (Code Review) 17 Jul '19

17 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33409 Change subject: nb/intel/x4x: Die on unknown memory speed ...................................................................... nb/intel/x4x: Die on unknown memory speed The speed argument should be one of the six values from the mem_clk enum, so something is very wrong if this is not the case. Better to die() now than return 0, which will cause a division-by-zero error later on where this function is called. Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1391088 --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33409/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 422b0ff..dae10cf 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -42,7 +42,7 @@ static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; if (speed >= ARRAY_SIZE(mhz)) - return 0; + die("RAM init: unknown DDR2 speed %u\n", speed); return mhz[speed]; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256 Gerrit-Change-Number: 33409 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 13

Change in ...coreboot[master]: nb/intel/nehalem: Prevent out of bounds read
by Jacob Garber (Code Review) 17 Jul '19

17 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33383 Change subject: nb/intel/nehalem: Prevent out of bounds read ...................................................................... nb/intel/nehalem: Prevent out of bounds read Check that clock_speed_index is non-zero before decrementing it, else we will get a very large out of bounds array access. Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1229675 --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33383/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 15d6abb..72a2c57 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -598,7 +598,8 @@ for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { if (cycletime == min_cycletime[clock_speed_index]) break; - if (cycletime > min_cycletime[clock_speed_index]) { + if (cycletime > min_cycletime[clock_speed_index] && + clock_speed_index != 0) { clock_speed_index--; cycletime = min_cycletime[clock_speed_index]; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/33383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e Gerrit-Change-Number: 33383 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 14

Change in ...coreboot[master]: soc/amd/stoneyridge: Add merlinfalcon configuration
by Richard Spiegel (Code Review) 17 Jul '19

17 Jul '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33621 Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ...................................................................... soc/amd/stoneyridge: Add merlinfalcon configuration In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON_FP4) and modify makefile based on this config parameter. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 106 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ba82565..047379c 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,8 +23,14 @@ help AMD Stoney Ridge FT4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +config SOC_AMD_MERLINFALCON_FP4 + bool + help + AMD Merlin Falcon FP4 support +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON_FP4 + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 @@ -71,6 +77,55 @@ select SSE2 select RTC select SOC_AMD_PSP_SELECTABLE_SMU_FW +endif + +if SOC_AMD_MERLINFALCON_FP4 +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select X86_AMD_FIXED_MTRRS + select ACPI_AMD_HARDWARE_SLEEP_VALUES + select COLLECT_TIMESTAMPS_NO_TSC + select DRIVERS_I2C_DESIGNWARE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_SYNC_LFENCE + select COLLECT_TIMESTAMPS + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_S3 + select C_ENVIRONMENT_BOOTBLOCK + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select HAVE_SMI_HANDLER + select SMM_TSEG + select POSTCAR_STAGE + select POSTCAR_CONSOLE + select SSE2 + select RTC +endif config VBOOT select VBOOT_SEPARATE_VERSTAGE @@ -135,6 +190,7 @@ config VGA_BIOS_ID string + default "1002,9874" if SOC_AMD_MERLINFALCON_FP4 default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -142,6 +198,7 @@ config VGA_BIOS_FILE string + default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" if SOC_AMD_MERLINFALCON_FP4 default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -190,6 +247,7 @@ config AMD_PUBKEY_FILE string "AMD public Key" + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyMF.bin" if SOC_AMD_MERLINFALCON_FP4 default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE @@ -386,4 +444,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON_FP4 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..76c4f09 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -142,7 +142,11 @@ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y) +FIRMWARE_TYPE=MF +else FIRMWARE_TYPE=ST +endif ###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key @@ -214,7 +218,6 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ @@ -232,6 +235,45 @@ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ $(AMDFWTOOL) + +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ + $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUFIRMWARE2_FN_FILE) \ + $(OPT_SMUSCS_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --output $@ +endif + +ifeq ((CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ @@ -267,6 +309,7 @@ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ +endif ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw @@ -313,4 +356,4 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_MERLINFALCON_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/33621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Gerrit-Change-Number: 33621 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 27

Change in ...coreboot[master]: kodama: add a new configuration for Kodama.
by Peichao Li (Code Review) 16 Jul '19

16 Jul '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33616 Change subject: kodama: add a new configuration for Kodama. ...................................................................... kodama: add a new configuration for Kodama. This config file could be configured Kodama project and add panel driver for Kodama. BUG=b:135490566 BRANCH=None TEST=1. emerge-kukui coreboot depthcharge libpayload \ chromeos-bootimage 2. check coreboot binary could be generated under the /build/chroot/kukui/firmware/. Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946 --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/display.c A src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_kodama.c 6 files changed, 420 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33616/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 6831d1e..bb496d0 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -28,6 +28,7 @@ select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select FATAL_ASSERTS @@ -37,6 +38,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string @@ -47,6 +51,7 @@ default "Kukui" if BOARD_GOOGLE_KUKUI default "Krane" if BOARD_GOOGLE_KRANE default "Flapjack" if BOARD_GOOGLE_FLAPJACK + default "Kodama" if BOARD_GOOGLE_KODAMA config DRIVER_TPM_SPI_BUS hex @@ -66,5 +71,6 @@ default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI default "KRANE TEST 5417" if BOARD_GOOGLE_KRANE default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK + default "KODAMA TEST 3140" if BOARD_GOOGLE_KODAMA endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 348be66..d175c73 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -11,3 +11,7 @@ config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_KODAMA + bool "-> kodama" + select BOARD_GOOGLE_KUKUI_COMMON diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..bbfb90a 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -22,6 +22,11 @@ ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c +ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c +ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c +ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c +ramstage-&(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c new file mode 100644 index 0000000..c7f7f91 --- /dev/null +++ b/src/mainboard/google/kukui/display.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static void _display_startup(struct edid *edid, + struct lcm_init_table *init_table, + u32 init_table_size) +{ + int ret = 0; + u32 mipi_dsi_flags; + + if ((edid == NULL) || (init_table == NULL)) { + printk(BIOS_ERR, "%s: wrong parameters\n", __func__); + return; + } + + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM; + + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + + mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, edid, init_table, init_table_size); + + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + + mtk_ddp_mode_set(edid); + + set_vbe_mode_info_valid(edid, (uintptr_t)0); +} + +static struct edid *get_edid(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) + return info->edid; + return NULL; +} + +static struct lcm_init_table *get_panel_init_table(struct board_display_intf + *intf, u32 *table_size) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) { + *table_size = info->table_size; + return info->init_table; + } + + *table_size = 0; + return NULL; +} + +static const char *get_panel_name(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) + return info->panel_name; + return NULL; +} + +/* Exported Functions */ + +struct board_display_intf *get_current_display_intf(void) +{ + return &panel_display_intf; +} + +int update_panel_info(struct board_display_intf *intf) +{ + int i; + union panel_id id = intf->get_panel_id(intf); + + if (intf->is_panel_id_valid(id)) { + for (i = 0; i < intf->all_panel_info_size; ++i) { + if (id.value == intf->all_panel_info[i].disp_id.value) { + intf->cur_panel_info = &intf->all_panel_info[i]; + return 0; + } + } + } + return -1; +} + +void display_startup(struct board_display_intf *intf) +{ + struct edid *edid; + u32 init_table_size; + struct lcm_init_table *init_table; + + edid = get_edid(intf); + init_table = get_panel_init_table(intf, &init_table_size); + printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n", + __func__, get_panel_name(intf), init_table_size); + _display_startup(edid, init_table, init_table_size); +} diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h new file mode 100644 index 0000000..6262b8a --- /dev/null +++ b/src/mainboard/google/kukui/display.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_DISPLAY_H__ + +#include <soc/dsi.h> +#include <soc/gpio.h> + +#define MAKE_AS_A_STRING(arg) #arg + +enum kukui_panel_id { + PANEL_KUKUI_FIRST = 0, + PANEL_KUKUI_INNOLUX = 0, + PANEL_KUKUI_P097PFG_SSD2858, + PANEL_KUKUI_UNKNOWN, + PANEL_KUKUI_COUNT, + PANEL_KUKUI_UNINITIALIZED +}; + +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + +enum flapjack_panel_id { + PANEL_FLAPJACK_FIRST = 0, + PANEL_FLAPJACK_BOE_TV101WUM_NG0, + PANEL_FLAPJACK_BOE_TV080WUM_NG0, + PANEL_FLAPJACK_INX_OTA7290D10P, + PANEL_FLAPJACK_AUO_NT51021D8P, + PANEL_FLAPJACK_UNKNOWN, + PANEL_FLAPJACK_COUNT, + PANEL_FLAPJACK_UNINITIALIZED +}; + +enum kodama_panel_id { + PANEL_KODAMA_FIRST = 0, + PANEL_KODAMA_INNOLUX = 0, + PANEL_KODAMA_BOE_TV101WUM_NL2, + PANEL_KODAMA_UNKNOWN, + PANEL_KODAMA_COUNT, + PANEL_KODAMA_UNINITIALIZED +}; + +union panel_id { + enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; + enum flapjack_panel_id flapjack_panel; + enum kodama_panel_id kodama_panel; + int value; +}; + +struct panel_info { + union panel_id disp_id; /* the ID for panel */ + const char *panel_name; /* display panel name */ + int voltage; /* voltage of LCM_ID */ + struct edid *edid; /* edid info of this panel */ + struct lcm_init_table *init_table; /* init command table */ + u32 table_size; /* init command table size */ +}; + +#define PANEL(_panel_id, _voltage, _edid, _init_table) \ + { \ + .disp_id = {_panel_id},\ + .panel_name = MAKE_AS_A_STRING(_panel_id),\ + .voltage = _voltage,\ + .edid = &_edid,\ + .init_table = _init_table,\ + .table_size = ARRAY_SIZE(_init_table)} \ + + +struct board_display_intf { + const char *board; /* board name */ + struct panel_info *all_panel_info; /* all supported panel info */ + u32 all_panel_info_size; /* num of supported panel */ + /* + * Runtime member + */ + struct panel_info *cur_panel_info; /* detected panel info */ + /* + * board related functions + */ + + union panel_id (*get_panel_id)(struct board_display_intf *intf); + bool (*is_panel_id_valid)(union panel_id id); + int (*backlight)(struct board_display_intf *intf); + int (*power)(struct board_display_intf *intf); +}; + +/* + * Exported functions + */ + +struct board_display_intf *get_current_display_intf(void); +int update_panel_info(struct board_display_intf *intf); +void display_startup(struct board_display_intf *intf); + + +/* + * Panel Interface for boards + */ +extern struct board_display_intf panel_display_intf; + +#endif diff --git a/src/mainboard/google/kukui/panel_kodama.c b/src/mainboard/google/kukui/panel_kodama.c new file mode 100644 index 0000000..7efc88f --- /dev/null +++ b/src/mainboard/google/kukui/panel_kodama.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid kodama_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +static struct lcm_init_table lcm_init_cmd[] = { + {INIT_DCS_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE} }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON} }, + {DELAY_CMD, 120, {} }, +}; + +static struct edid kodama_TV101WUM_NL2_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159391, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 142, .y_mm = 228, + }, +}; + +struct lcm_init_table lcm_TV101WUM_NL2_init_cmd[] = { + // full HD + {INIT_DCS_CMD, 1, {0x11} }, + {DELAY_CMD, 800, {} }, + {INIT_DCS_CMD, 2, {0x36, 0x03} }, + {INIT_DCS_CMD, 1, {0x29} }, + {DELAY_CMD, 20, {} }, + {INIT_DCS_CMD, 2, {0x85, 0x04} }, + {INIT_DCS_CMD, 2, {0x86, 0x08} }, + {INIT_DCS_CMD, 2, {0x83, 0xAA} }, + {INIT_DCS_CMD, 2, {0x84, 0x11} }, + {INIT_DCS_CMD, 2, {0x98, 0x12} }, +}; + +struct panel_info kodama_panel_info[] = { + PANEL(PANEL_KODAMA_INNOLUX, + 74000, + kodama_innolux_edid, + lcm_init_cmd), + PANEL(PANEL_KODAMA_BOE_TV101WUM_NL2, + 212000, + kodama_TV101WUM_NL2_edid, + lcm_TV101WUM_NL2_init_cmd), + {{PANEL_KODAMA_UNKNOWN}, "PANEL_KODAMA_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id kodama_get_panel_id(struct board_display_intf *intf) +{ + if (board_id() < 2) + return (union panel_id)PANEL_KODAMA_INNOLUX; + else { + printk(BIOS_ERR, "WPC DEBUG enter kodama driver\n"); + return (union panel_id)PANEL_KODAMA_BOE_TV101WUM_NL2; + } +}; + +static bool kodama_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KODAMA_UNKNOWN) + return true; + return false; +}; + +static int kodama_backlight(struct board_display_intf *intf) +{ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ + + return 0; +}; + +static int kodama_power(struct board_display_intf *intf) +{ + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + gpio_output(GPIO(BPI_BUS3), 0); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + gpio_output(GPIO(BPI_OLAT1), 1); + gpio_output(GPIO(SIM2_SCLK), 1); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + gpio_output(GPIO(BPI_BUS3), 1); + mdelay(20); + } + + return 0; + +}; + +struct board_display_intf panel_display_intf = { + .board = "kodama", + .all_panel_info = kodama_panel_info, + .all_panel_info_size = ARRAY_SIZE(kodama_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &kodama_get_panel_id, + .is_panel_id_valid = &kodama_is_panel_id_valid, + .backlight = &kodama_backlight, + .power = &kodama_power, +}; + -- To view, visit https://review.coreboot.org/c/coreboot/+/33616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946 Gerrit-Change-Number: 33616 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

7 34

Change in ...coreboot[master]: sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized reads
by Jacob Garber (Code Review) 16 Jul '19

16 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33790 Change subject: sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized reads ...................................................................... sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized reads "There are two hard things in computer science: cache invalidation, naming things, and off-by-one errors." var_num records the number of initialized entries in the reg_var array. However, this means the index of the last initialized element is one less than the value of var_num, so we need to take that into account when indexing into the array. This has already been fixed in several other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here. Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: scan-build 8.0.0 --- M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb900/lpc.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb800/lpc.c 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33790/1 diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a88d6d3..483d185 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -170,11 +170,11 @@ pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + case 1: //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index b04ecfa..8fcb947 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -168,11 +168,11 @@ pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + case 1: //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 6f3be03..b7f0dc3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -228,11 +228,11 @@ pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; } diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 649add5..74b6374 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -220,11 +220,11 @@ pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317 Gerrit-Change-Number: 33790 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/icelake: Add option to enable display over PCI external GFX
by Subrata Banik (Code Review) 14 Jul '19

14 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33739 Change subject: soc/intel/icelake: Add option to enable display over PCI external GFX ...................................................................... soc/intel/icelake: Add option to enable display over PCI external GFX This patch selects FSP UPDs required for internal and external GFX bring up based on CONFIG_ENABLE_EXT_GFX Kconfig. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/romstage/fsp_params.c 2 files changed, 38 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33739/1 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ac7edd2..2792d26 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -80,9 +80,24 @@ mainboard_silicon_init_params(params); - params->PeiGraphicsPeimInit = 1; - params->GtFreqMax = 2; - params->CdClock = 3; + dev = pcidev_on_root(2, 0); + + if (!dev || !dev->enabled) { + /* + * If iGPU is disabled or not defined in the devicetree.cb, + * the FSP does not initialize this device + */ + params->PeiGraphicsPeimInit = 0; + if (CONFIG(ENABLE_EXT_GFX)) { + params->Enable8254ClockGating = 0; + params->Enable8254ClockGatingOnS3 = 0; + } + } else { + params->PeiGraphicsPeimInit = 1; + params->GtFreqMax = 2; + params->CdClock = 3; + } + /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 3c49fee..415c039 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -25,17 +25,34 @@ const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev = pcidev_on_root(0, 0); + const struct device *dev = pcidev_on_root(2, 0); uint32_t mask = 0; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + if (!dev || !dev->enabled) { + /* + * If iGPU is disabled or not defined in the devicetree.cb, + * the FSP does not initialize this device + */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + if (CONFIG(ENABLE_EXT_GFX)) { + m_cfg->ScanExtGfxForLegacyOpRom = 1; + m_cfg->PrimaryDisplay = 2; + } + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; m_cfg->SkipMbpHob = 1; + + dev = pcidev_on_root(0x1f, 3); /* If Audio Codec is enabled, enable FSP UPD */ if (!dev) m_cfg->PchHdaEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Gerrit-Change-Number: 33739 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

8 44

Change in ...coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32341 Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 693e278e: 2018-02-01 18:15:53 +0000 - (Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch) to commit id 5d149bdb: 2019-04-16 14:48:55 +0100 - (Temporarily disable shared Mbed TLS heap for SGM) This brings in 2316 new commits. Change-Id: Iaeec22d062e451f014b1800b473bfda94fa40530 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32341/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..5d149bd 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit 5d149bdb18c0c6fb0aa76f32e0ffbb9f9269c994 -- To view, visit https://review.coreboot.org/c/coreboot/+/32341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeec22d062e451f014b1800b473bfda94fa40530 Gerrit-Change-Number: 32341 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: Update chromeec submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32342 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 11bd4c0f4: 2018-05-22 21:57:16 -0700 - (bip: enabled PPC interrupts) to commit id 8841b815c: 2019-04-17 13:33:39 +0000 - (ish: add missing EOI in LAPIC error irq handler) This brings in 2056 new commits. Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32342/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..8841b81 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 8841b815c195aadacb8f0f6e625041c3427bbd97 -- To view, visit https://review.coreboot.org/c/coreboot/+/32342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Gerrit-Change-Number: 32342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: Update fsp submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32343 Change subject: Update fsp submodule to upstream master ...................................................................... Update fsp submodule to upstream master Updating from commit id 162719b: 2018-09-27 10:55:19 -0700 - (Add SplitFspBin.py) to commit id 8699794: 2019-04-04 15:19:28 -0700 - (Denverton-NS Production Validated 004) This brings in 10 new commits. Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32343/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 162719b..8699794 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 +Subproject commit 86997945d03e1471f5dcdbbbb8d6118e5a6ecd38 -- To view, visit https://review.coreboot.org/c/coreboot/+/32343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Gerrit-Change-Number: 32343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019