coreboot-gerrit June 2019

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Change in ...coreboot[master]: libpayload/libc: Correct strlcat return value
by Jacob Garber (Code Review) 23 Jul '19

23 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33787 Change subject: libpayload/libc: Correct strlcat return value ...................................................................... libpayload/libc: Correct strlcat return value The documented return value for strlcat is horribly wrong, as is the return value itself. It should not return the number of appended bytes, but rather the total size of the concatenated string. From the man page: The strlcpy() and strlcat() functions return the total length of the string they tried to create. For strlcpy() that means the length of src. For strlcat() that means the initial length of dst plus the length of src. While this may seem somewhat confusing, it was done to make truncation detection simple. Change-Id: I4421305af85bce88d12d6fdc2eea6807ccdcf449 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/libc/string.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33787/1 diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 6c257cb..bd795f4 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -249,7 +249,7 @@ * @param d The destination string. * @param s The source string. * @param n d will have at most n-1 characters (plus NUL) after invocation. - * @return A pointer to the destination string. + * @return The total length of the string that would have been created. */ size_t strlcat(char *d, const char *s, size_t n) { @@ -264,7 +264,7 @@ p[i] = s[i]; p[i] = '\0'; - return max; + return sl + dl; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/33787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4421305af85bce88d12d6fdc2eea6807ccdcf449 Gerrit-Change-Number: 33787 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: src/lib/hexdump: Use size_t for lengths
by HAOUAS Elyes (Code Review) 23 Jul '19

23 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33799 Change subject: src/lib/hexdump: Use size_t for lengths ...................................................................... src/lib/hexdump: Use size_t for lengths Change-Id: I29a7ae8c499bb1e8ab7c8741b2dfb7663d82a362 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/hexdump.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33799/1 diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 1e689e3..511dedd 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -19,14 +19,13 @@ void hexdump(const void *memory, size_t length) { - int i; + size_t i, j; uint8_t *line; int all_zero = 0; int all_one = 0; size_t num_bytes; for (i = 0; i < length; i += 16) { - int j; num_bytes = MIN(length - i, 16); line = ((uint8_t *)memory) + i; -- To view, visit https://review.coreboot.org/c/coreboot/+/33799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a7ae8c499bb1e8ab7c8741b2dfb7663d82a362 Gerrit-Change-Number: 33799 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 15

Change in ...coreboot[master]: coreboot: add md power off flow
by Yanjie Jiang (Code Review) 23 Jul '19

23 Jul '19

Yanjie Jiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32666 Change subject: coreboot: add md power off flow ...................................................................... coreboot: add md power off flow Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/mt8183.c 4 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc old mode 100644 new mode 100755 index 5392a9e..ca7d521 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += md_ctrl.c decompressor-y += decompressor.c decompressor-y += ../common/mmu_operations.c @@ -21,6 +22,7 @@ verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +verstage-y += md_ctrl.c romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c @@ -39,6 +41,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c +romstage-y += md_ctrl.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h new file mode 100755 index 0000000..534de9b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MD_POWER_H__ +#define __SOC_MEDIATEK_MD_POWER_H__ + +void mtk_md_early_init(void); + +#endif \ No newline at end of file diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100755 index 0000000..c8acb1f --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/md_ctrl.h> + +static void internal_md1_power_down(void) +{ + unsigned int reg_value; + + /* 1. md clock setting: gating */ + reg_value = read32(&mtk_topckgen->clk_mode); + reg_value |= ((1<<8)|(1<<9)); + write32(&mtk_topckgen->clk_mode, reg_value); + + /* 2. mixedsys topsm init, for release srcclkena in kernel */ + reg_value = read32(&mt8183_infracfg->infra_misc2); + reg_value &= ~0xFF; + write32(&mt8183_infracfg->infra_misc2, reg_value); + + printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n", + read32(&mt8183_infracfg->infra_misc2)); +} + +void mtk_md_early_init(void) +{ + internal_md1_power_down(); +} + diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c old mode 100644 new mode 100755 index c441980..66038e3 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@ #include <soc/mt8183.h> #include <soc/wdt.h> +#include <soc/md_ctrl.h> void mt8183_early_init(void) { mtk_wdt_init(); + mtk_md_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Gerrit-Change-Number: 32666 Gerrit-PatchSet: 1 Gerrit-Owner: Yanjie Jiang <yanjie.jiang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: google/kukui: boot up sspm
by Erin Lo (Code Review) 22 Jul '19

22 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31516 Change subject: google/kukui: boot up sspm ...................................................................... google/kukui: boot up sspm Load sspm firmware form cbfs and bring up it. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/sspm.h A src/soc/mediatek/mt8183/sspm.c 7 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31516/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..0dcdb20 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -65,4 +65,8 @@ default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK +config SSPM_BIN_FILE + string "SSPM BIN FILE" + default "" + endif diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..565c3f7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm +sspm-file := $(call strip_quotes,$(CONFIG_SSPM_BIN_FILE)) +sspm-type := raw +sspm-compression :=$(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..5aaab8b 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <cbfs.h> #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/usb.h> +#include <soc/sspm.h> static void configure_emmc(void) { @@ -37,10 +40,29 @@ setup_usb_host(); } +#define BUF_SIZE (64 * KiB) +unsigned char buf[BUF_SIZE]; + +static void sspm_boot(void) +{ + size_t fw_size = cbfs_boot_load_file("sspm", buf, sizeof(buf), + CBFS_TYPE_RAW); + + if (fw_size == 0) + printk(BIOS_DEBUG, "no sspm\n"); + else + printk(BIOS_DEBUG, "sspm[0]=%#x, [%zd]=%#x\n", + buf[0], fw_size - 1, buf[fw_size - 1]); + + sspm_init(buf, BUF_SIZE); + +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + sspm_boot(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..199b22d 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += sspm.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..f812224 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,7 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SSPM_BASE = IO_PHYS + 0x00440000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h new file mode 100644 index 0000000..f006ca2 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SSPM_H +#define SOC_MEDIATEK_MT8183_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_sspm_regs { + u32 sw_rstn; +}; +static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_BASE; +#define CFG_SSPM_SRAM 0x10400000 +s32 sspm_init(unsigned char *buf, int len); +#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c new file mode 100644 index 0000000..a42a0f5 --- /dev/null +++ b/src/soc/mediatek/mt8183/sspm.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/sspm.h> +#include <string.h> + +#define SSPM_UART 1 +s32 sspm_init(unsigned char *buf, int len) +{ + memcpy((void*)CFG_SSPM_SRAM, buf, len); +#if SSPM_UART + gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SSPM_UTXD_AO); + gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SSPM_URXD_AO); +#endif + mb(); + write32(&mt8183_sspm->sw_rstn, 0x1); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Gerrit-Change-Number: 31516 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

9 67

Change in ...coreboot[master]: soc/amd/picasso: Make romstage a hybrid
by Marshall Dawson (Code Review) 22 Jul '19

22 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33760 Change subject: soc/amd/picasso: Make romstage a hybrid ...................................................................... soc/amd/picasso: Make romstage a hybrid Update romstage.c and associated files to create the hybrid romstage. Make early calls to set up the soc and any mainboard requirements, similar to what bootblock does in other x86 systems. Implementation details are in Documentation/soc/amd/family17h.md. Change-Id: I2c3dc68463d2027d2b1e68e15708cfb6a84f1b39 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c 3 files changed, 119 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33760/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7bc1810..1facf64 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,8 +18,8 @@ #include <device/device.h> -#define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_TEMPRAM 2 +#define SOC_EARLY_VMTRR_ROMSTAGE 0 +#define SOC_EARLY_VMTRR_TEMPRAM 1 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index d8b2900..fca8f0c 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2018 Google LLC + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,19 @@ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__ -void mainboard_romstage_entry(int s3_resume); +#include <stdint.h> + +#if (CONFIG_ROMSTAGE_ADDR + CONFIG_ROMSTAGE_MAX_SIZE) & 0xffff +# error Top of the BIOS binary image must be 64KB aligned +#endif + +struct early_saved_info { + uint32_t unused; + uint32_t bist; + uint64_t early_tsc; +} __packed; + +void romstage_mainboard_early_init(void); +void romstage_mainboard_init(int s3_resume); #endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 950b41f..da4ed8d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify @@ -17,25 +17,67 @@ #include <device/pci_ops.h> #include <arch/cpu.h> #include <arch/acpi.h> +#include <arch/exception.h> +#include <arch/symbols.h> +#include <delay.h> +#include <pc80/mc146818rtc.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/msr.h> #include <cbmem.h> -#include <commonlib/helpers.h> #include <console/console.h> -#include <device/device.h> +#include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> +#include <soc/cpu.h> #include <soc/northbridge.h> -#include <soc/romstage.h> #include <soc/southbridge.h> +#include <soc/romstage.h> -#include "chip.h" +__weak void romstage_mainboard_early_init(void) {} +__weak void romstage_mainboard_init(int s3_resume) {} -void __weak mainboard_romstage_entry(int s3_resume) +static void romstage_soc_early_init(void) { - /* By default, don't do anything */ + msr_t mmconf; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); + + fch_pre_init(); +} + +static void romstage_soc_init(int s3_resume) +{ + fch_early_init(); +} + +static uint32_t find_bist(void) +{ + volatile struct early_saved_info *early; + + early = (volatile struct early_saved_info *)_car_stack_end - 1; + return early->bist; +} + +static void init_timestamps(tsc_t tsc) +{ + volatile struct early_saved_info *early; + uint64_t stage_start; + + /* don't rely on tsc_t ordering */ + stage_start = (uint64_t)tsc.hi << 32; + stage_start += tsc.lo; + + early = (volatile struct early_saved_info *)_car_stack_end - 1; + timestamp_init(early->early_tsc); + timestamp_add(TS_START_ROMSTAGE, stage_start); } asmlinkage void car_stage_entry(void) @@ -45,29 +87,67 @@ void *smm_base; size_t smm_size; uintptr_t tseg_base; - int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + int s3_resume; + tsc_t tsc = rdtsc(); + post_code(0x40); + /* + * Many of these tasks typically happen in bootblock, but execution + * begins in romstage for this device. + */ + + /* cache this code and the memory used to mimic TEMPRAM */ + set_var_mtrr(SOC_EARLY_VMTRR_ROMSTAGE, CONFIG_ROMSTAGE_ADDR, + CONFIG_ROMSTAGE_MAX_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(SOC_EARLY_VMTRR_TEMPRAM, CONFIG_DCACHE_RAM_BASE, + CONFIG_DCACHE_RAM_SIZE, MTRR_TYPE_WRBACK); + + romstage_soc_early_init(); + romstage_mainboard_early_init(); + + post_code(0x41); + init_timer(); + sanitize_cmos(); + cmos_post_init(); + + post_code(0x42); console_init(); - mainboard_romstage_entry(s3_resume); - - if (!s3_resume) { - post_code(0x40); - - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); - } else { - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - } - post_code(0x43); + report_bist_failure(find_bist()); + + post_code(0x44); + if (CONFIG(COLLECT_TIMESTAMPS)) + init_timestamps(tsc); + + post_code(0x45); + exception_init(); + + post_code(0x46); + s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + romstage_soc_init(s3_resume); + romstage_mainboard_init(s3_resume); + + post_code(0x47); + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + post_code(0x48); + if (!s3_resume && CONFIG(ELOG_BOOT_COUNT)) + boot_count_increment(); + + post_code(0x49); + msr_t tom = rdmsr(TOP_MEM); + tom.lo &= ~0xffffff; + backup_top_of_low_cacheable(tom.lo); + + post_code(0x4a); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); - post_code(0x44); + post_code(0x4b); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); @@ -94,7 +174,7 @@ tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); - post_code(0x45); + post_code(0x4c); run_postcar_phase(&pcf); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c3dc68463d2027d2b1e68e15708cfb6a84f1b39 Gerrit-Change-Number: 33760 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: mediatek/mt8183: support SANDISK LPDDR4X DDR bootup
by huayang duan (Code Review) 21 Jul '19

21 Jul '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33838 Change subject: mediatek/mt8183: support SANDISK LPDDR4X DDR bootup ...................................................................... mediatek/mt8183: support SANDISK LPDDR4X DDR bootup Support SANDISK SDADA4CR-128G EMCP LPDDR4X DDR BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I7de4c9a27282d3d00f51adf46dcb3d2f3984bfff --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33838/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 5931c79..202a75f6 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -23,6 +23,7 @@ [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 77158a5..40e3641 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -3,6 +3,7 @@ sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB +sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c new file mode 100755 index 0000000..61060d6 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, + [ODT_ON] = {0x9, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, + [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x3, 0x3}, + [CHANNEL_B] = {0x4, 0x6} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x5C, 0x5A}, + [CHANNEL_B] = {0x5C, 0x5A} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/33838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7de4c9a27282d3d00f51adf46dcb3d2f3984bfff Gerrit-Change-Number: 33838 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 12

Change in ...coreboot[master]: mediatek/mt8183: Calibration RTC eosc clock
by Ran Bi (Code Review) 21 Jul '19

21 Jul '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33907 Change subject: mediatek/mt8183: Calibration RTC eosc clock ...................................................................... mediatek/mt8183: Calibration RTC eosc clock Calibration RTC eosc clock which will be used when RTC go into low power state. BUG=b:133872611 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 2 files changed, 187 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33907/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 841a202..e7ab18e 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -128,6 +128,9 @@ /* PMIC TOP Register Definition */ enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, PMIC_RG_TOP_CKPDN_CON1 = 0x0112, PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, @@ -154,6 +157,56 @@ PMIC_RG_TOP_TMA_KEY = 0x03A8 }; +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013E, + PMIC_RG_FQMTR_CON0 = 0x0514, + PMIC_RG_FQMTR_WINSET = 0x0516, + PMIC_RG_FQMTR_DATA = 0x0518, + + FQMTR_TIMEOUT_US = 8000 +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0 +}; + +enum { + PMIC_FQMTR_RST = 1U << 8 +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15 +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2 +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f +}; + /* external API */ void rtc_bbpu_power_on(void); void rtc_osc_init(void); diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 1e944ad..4da4175 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -19,6 +19,7 @@ #include <soc/rtc.h> #include <soc/mt6358.h> #include <soc/pmic_wrap.h> +#include <timer.h> #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) @@ -79,11 +80,141 @@ return rtc_write_trigger(); } -/* set xosc mode */ +static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + struct stopwatch sw; + + if (val != 0) { + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | (val & RTC_XOSCCALI_MASK)); + } + + /* enable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, 10); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, 11); + + /* FQMTR reset */ + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + rtc_write(PMIC_RG_FQMTR_RST, fqmtr_rst | PMIC_FQMTR_RST); + do { + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + } while (fqmtr_data && (PMIC_FQMTR_CON0_BUSY & fqmtr_busy)); + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + /* FQMTR normal */ + rtc_write(PMIC_RG_FQMTR_RST, fqmtr_rst & ~PMIC_FQMTR_RST); + + /* set freq. meter window value (0=1X32K(fix clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* enable 26M -> delay 100us -> enable FQMTR */ + udelay(100); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + udelay(100); + + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + do { + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + if (stopwatch_expired(&sw)) { + rtc_info("get frequency time out !!\n"); + return 0; + } + } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); + + /* read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* disable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* disable FQMTR -> delay 100us -> disable 26M */ + udelay(100); + /* disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input=0x%x, ouput=%d\n", val, fqmtr_data); + + /* disable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, 10); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, 11); + + return fqmtr_data; +} + +/* 32k clock calibration */ +static u16 rtc_eosc_cali(void) +{ + u16 middle, diff1, diff2, cksel; + u16 val = 0; + u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; + + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + cksel &= ~PMIC_FQMTR_CKSEL_MASK; + /* select EOSC_32 as fixed clock */ + rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel); + + while (left <= right) { + middle = (right + left) / 2; + if (middle == left) + break; + + /* select 26M as target clock */ + val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); + + if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + break; + if (val > RTC_FQMTR_HIGH_BASE) + right = middle; + else + left = middle; + } + + if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + return middle; + + val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val > RTC_FQMTR_LOW_BASE) + diff1 = val - RTC_FQMTR_LOW_BASE; + else + diff1 = RTC_FQMTR_LOW_BASE - val; + + val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val > RTC_FQMTR_LOW_BASE) + diff2 = val - RTC_FQMTR_LOW_BASE; + else + diff2 = RTC_FQMTR_LOW_BASE - val; + + if (diff1 < diff2) + return left; + else + return right; +} + +/* set eosc clock */ void rtc_osc_init(void) { + u16 osc32con; + /* enable 32K export */ rtc_gpio_init(); + + /* eosc32 calibration for powerdown clock */ + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~RTC_XOSCCALI_MASK; + osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; + rtc_xosc_write(osc32con); + rtc_info("EOSC32 cali val = 0x%x\n", osc32con); } /* enable lpd subroutine */ @@ -196,6 +327,8 @@ goto err; } + rtc_osc_init(); + if (recover) mdelay(20); -- To view, visit https://review.coreboot.org/c/coreboot/+/33907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c Gerrit-Change-Number: 33907 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

6 9

Change in ...libgfxinit[master]: gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31453 Change subject: gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake ...................................................................... gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake These seem to be 100% compatible to Kaby Lake wrt. modesetting. So treat them as the latter for now. Untested. Didn't look at documented workarounds, yet. Change-Id: If01883ba95246f9bfd66049772597e0317e294d2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/53/31453/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index d91d9c7..c3f3a7c 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -390,6 +390,14 @@ (Device_Id and 16#ffcf#) = 16#590b# or (Device_Id and 16#ffcf#) = 16#590d#); + function Is_Coffee_Lake_Y_AML (Device_Id : Word16) return Boolean is + (Device_Id = 16#87ca#); + -- Including Whiskey Lake: + function Is_Coffee_Lake_U (Device_Id : Word16) return Boolean is + ((Device_Id and 16#fff0#) = 16#3ea0#); + function Is_Coffee_Lake (Device_Id : Word16) return Boolean is + ((Device_Id and 16#fff0#) = 16#3e90#); + function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant) return Boolean is (case CPU is @@ -412,10 +420,16 @@ when ULT => Is_Skylake_U (Device_Id), when ULX => Is_Skylake_Y (Device_Id)), when Kabylake => (case CPU_Var is - when Normal => Is_Kaby_Lake (Device_Id), - when ULT => Is_Kaby_Lake_U (Device_Id), - when ULX => Is_Kaby_Lake_Y (Device_Id) or - Is_Kaby_Lake_Y_AML (Device_Id))); + when Normal => + Is_Kaby_Lake (Device_Id) or + Is_Coffee_Lake (Device_Id), + when ULT => + Is_Kaby_Lake_U (Device_Id) or + Is_Coffee_Lake_U (Device_Id), + when ULX => + Is_Kaby_Lake_Y (Device_Id) or + Is_Kaby_Lake_Y_AML (Device_Id) or + Is_Coffee_Lake_Y_AML (Device_Id))); function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If01883ba95246f9bfd66049772597e0317e294d2 Gerrit-Change-Number: 31453 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 14

Change in ...libgfxinit[master]: dp training: Write correct training data when switching patterns
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32732 Change subject: dp training: Write correct training data when switching patterns ...................................................................... dp training: Write correct training data when switching patterns Apparently this was wrong all the time. When switching the training pattern, i.e. writes to DPCD+0x102, we also have to write the current signal levels to subsequent offsets. We always wrote 0s in this case, even if we already negotiated higher values during the clock-recovery phase. Obviously, this results in havoc if the sink takes the 0s serious. Change-Id: I6ae2f9aaec0b042e8dee6e8b0099ea62c82f611b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-dp_training.adb 1 file changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/32/32732/1 diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb index 079d49c..d613d85 100644 --- a/common/hw-gfx-dp_training.adb +++ b/common/hw-gfx-dp_training.adb @@ -113,9 +113,10 @@ end Sink_Init; procedure Sink_Set_Training_Pattern - (DP : in Aux_T; + (Port : in T; Link : in DP_Link; Pattern : in DP_Info.Training_Pattern; + Train_Set : in DP_Info.Train_Set; Success : out Boolean) is use type DP_Info.Training_Pattern; @@ -124,21 +125,21 @@ TP : constant TP_Array := TP_Array' (DP_Info.TP_1 => 16#21#, DP_Info.TP_2 => 16#22#, DP_Info.TP_3 => 16#23#, DP_Info.TP_Idle => 16#00#, DP_Info.TP_None => 16#00#); + T_Set : constant Word8 := Training_Set (Port, Train_Set); Data : DP_Defs.Aux_Payload; Length : Positive := 1; begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Data := - (0 => TP (Pattern), - others => 0); -- Don't care - + Data := (TP (Pattern), others => 0); if Pattern < DP_Info.TP_Idle then Length := Length + Lane_Count (Link); + Data (1 .. Lane_Count (Link)) := (others => T_Set); end if; + Aux_Ch.Aux_Write - (Port => DP, + (Port => To_Aux (Port), Address => 16#00102#, -- TRAINING_PATTERN_SET Length => Length, Data => Data, @@ -332,7 +333,8 @@ pragma Warnings (GNATprove, On, """Success"" modified by call, but value overwritten*"); if Success then - Sink_Set_Training_Pattern (DP, Link, DP_Info.TP_1, Success); + Sink_Set_Training_Pattern + (Port, Link, DP_Info.TP_1, Train_Set, Success); end if; if Success then @@ -365,7 +367,7 @@ if Success then Set_Pattern (Port, Link, EQ_Pattern); - Sink_Set_Training_Pattern (DP, Link, EQ_Pattern, Success); + Sink_Set_Training_Pattern (Port, Link, EQ_Pattern, Train_Set, Success); end if; if Success then @@ -385,7 +387,7 @@ -- Set_Pattern (TP_None) includes sending the Idle Pattern, -- so tell sink first. Sink_Set_Training_Pattern - (DP, Link, DP_Info.TP_None, Success); + (Port, Link, DP_Info.TP_None, Train_Set, Success); Set_Pattern (Port, Link, DP_Info.TP_None); Success := Success and then EQ_Done; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I6ae2f9aaec0b042e8dee6e8b0099ea62c82f611b Gerrit-Change-Number: 32732 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 7

Change in ...libgfxinit[master]: dp training: Always end with normal output
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32731 Change subject: dp training: Always end with normal output ...................................................................... dp training: Always end with normal output The DP spec mandates that we return to normal output when we abandon a failed training, before we disable the output. However, the sequence suggested by Intel always disables the output, even if we try another time or another frequency. So we also always return to normal frame delivery. Change-Id: Ie1f19f2e1d1af62b402ad1dc41373d3d4437e976 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-dp_training.adb 1 file changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/31/32731/1 diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb index a2d00a7..079d49c 100644 --- a/common/hw-gfx-dp_training.adb +++ b/common/hw-gfx-dp_training.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2015-2016, 2019 secunet Security Networks AG -- Copyright (C) 2017 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify @@ -382,20 +382,14 @@ end loop; end if; - if Success then - if EQ_Done then - -- Set_Pattern (TP_None) includes sending the Idle Pattern, - -- so tell sink first. - Sink_Set_Training_Pattern - (DP, Link, DP_Info.TP_None, Success); - else - Success := False; - end if; - end if; + -- Set_Pattern (TP_None) includes sending the Idle Pattern, + -- so tell sink first. + Sink_Set_Training_Pattern + (DP, Link, DP_Info.TP_None, Success); + Set_Pattern (Port, Link, DP_Info.TP_None); - if Success then - Set_Pattern (Port, Link, DP_Info.TP_None); - else + Success := Success and then EQ_Done; + if not Success then Off (Port); end if; end Train_DP; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie1f19f2e1d1af62b402ad1dc41373d3d4437e976 Gerrit-Change-Number: 32731 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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