coreboot-gerrit June 2019

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Change in ...coreboot[master]: DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is ...
by Peichao Li (Code Review) 05 Aug '19

05 Aug '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33184 Change subject: DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is not final soultion of Bitland kukui project. ...................................................................... DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is not final soultion of Bitland kukui project. *** DO NOT SUBMIT *** Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I1191b33c63ba9947e700670882a048b014fb7c27 --- M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/display.c A src/mainboard/google/kukui/display.h M src/mainboard/google/kukui/mainboard.c A src/mainboard/google/kukui/panel_bitland.c 5 files changed, 382 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33184/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..49f09c7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -22,6 +22,9 @@ ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c +ramstage-y += panel_bitland.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c new file mode 100644 index 0000000..68042d5 --- /dev/null +++ b/src/mainboard/google/kukui/display.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> +#include "display.h" +#include "gpio.h" + +static void _display_startup(struct edid *edid, + struct lcm_init_table *init_table, + u32 init_table_size) +{ + int ret = 0; + u32 mipi_dsi_flags; + if ((edid == NULL) || (init_table == NULL)) { + printk(BIOS_ERR, "%s: wrong parameters\n", __func__); + return; + } + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, edid, init_table, init_table_size); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, (uintptr_t) 0); +} + +static struct edid *get_edid(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) + return info->edid; + return NULL; +} + +static struct lcm_init_table *get_panel_init_table(struct board_display_intf + *intf, u32 *table_size) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) { + *table_size = info->table_size; + return info->init_table; + } + *table_size = 0; + return NULL; +} + +static const char *get_panel_name(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) + return info->panel_name; + return NULL; +} + +/* Exported Functions */ +struct board_display_intf *get_current_display_intf(void) +{ + return &bitland_panel_display_intf; +} + +int update_panel_info(struct board_display_intf *intf) +{ + int i; + union panel_id id = intf->get_panel_id(intf); + if (intf->is_panel_id_valid(id)) { + for (i = 0; i < intf->all_panel_info_size; ++i) { + if (id.value == intf->all_panel_info[i].disp_id.value) { + intf->cur_panel_info = &intf->all_panel_info[i]; + return 0; + } + } + } + return ERR; +} + +void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +void display_startup(struct board_display_intf *intf) +{ + struct edid *edid; + u32 init_table_size; + struct lcm_init_table *init_table; + edid = get_edid(intf); + init_table = get_panel_init_table(intf, &init_table_size); + printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n", + __func__, get_panel_name(intf), init_table_size); + _display_startup(edid, init_table, init_table_size); +} + diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h new file mode 100644 index 0000000..1e65720 --- /dev/null +++ b/src/mainboard/google/kukui/display.h @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_DISPLAY_H__ + +#include <soc/dsi.h> +#include <soc/gpio.h> + +#define ERR (-1) +#define OK (1) + +#define MAKE_AS_A_STRING(arg) #arg + +enum kukui_panel_id { + PANEL_KUKUI_FIRST = 0, + PANEL_KUKUI_INNOLUX = 0, + PANEL_KUKUI_P097PFG_SSD2858, + PANEL_KUKUI_UNKNOWN, + PANEL_KUKUI_COUNT, + PANEL_KUKUI_UNINITIALIZED +}; + +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_BOE_TV101WUM_NL2, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + + +union panel_id { + enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; + int value; +}; + +struct panel_info { + union panel_id disp_id; /* the ID for panel */ + const char *panel_name; /* display panel name */ + int voltage; /* voltage of LCM_ID */ + struct edid *edid; /* edid info of this panel */ + struct lcm_init_table *init_table; /* init command table */ + u32 table_size; /* init command table size */ +}; + +#define PANEL(_panel_id, _voltage, _edid, _init_table) \ + { \ + .disp_id = {_panel_id},\ + .panel_name = MAKE_AS_A_STRING(_panel_id),\ + .voltage = _voltage,\ + .edid = &_edid,\ + .init_table = _init_table,\ + .table_size = ARRAY_SIZE(_init_table)} \ + + +struct board_display_intf { + const char *board; /* board name */ + struct panel_info *all_panel_info; /* all supported panel info */ + u32 all_panel_info_size; /* num of supported panel */ + /* + * Runtime member + */ + struct panel_info *cur_panel_info; /* detected panel info */ + /* + * board related functions + */ + + union panel_id (*get_panel_id)(struct board_display_intf *intf); + bool (*is_panel_id_valid)(union panel_id id); + int (*backlight)(struct board_display_intf *intf); + int (*power)(struct board_display_intf *intf); +}; + +/* + * Exported functions + */ + +struct board_display_intf *get_current_display_intf(void); +int update_panel_info(struct board_display_intf *intf); +void configure_backlight(void); +void display_startup(struct board_display_intf *intf); + + +/* + * Panel Interface for boards + */ +extern struct board_display_intf bitland_panel_display_intf; + +#endif + diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 40b8a49..aea91cb 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -14,10 +14,15 @@ */ #include <device/device.h> +#include <soc/bl31_plat_params.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> #include <soc/usb.h> +#include <console/console.h> +#include "display.h" +#include "gpio.h" + static void configure_emmc(void) { @@ -49,11 +54,37 @@ gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); } + +static void register_reset_to_bl31(void) +{ + static struct bl31_gpio_param param_reset = { + .h = { + .type = PARAM_RESET, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_HIGH, + }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_param(&param_reset.h); +} + static void mainboard_init(struct device *dev) { + struct board_display_intf *intf; + intf = get_current_display_intf(); + if (intf != NULL) { + display_startup(intf); + } else { + printk(BIOS_INFO, "Display init failure.\n"); + } + configure_emmc(); configure_usb(); configure_audio(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/kukui/panel_bitland.c b/src/mainboard/google/kukui/panel_bitland.c new file mode 100644 index 0000000..955c117 --- /dev/null +++ b/src/mainboard/google/kukui/panel_bitland.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 bitland tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid kukui_boe_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159391, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 142, .y_mm = 228, + }, +}; + +struct lcm_init_table lcm_boe_init_cmd[] = { + /* For full HD */ + {INIT_DCS_CMD, 1, {0x11} }, + {DELAY_CMD, 800, {} }, + {INIT_DCS_CMD, 2, {0x36, 0x03} }, + {INIT_DCS_CMD, 1, {0x29} }, + {DELAY_CMD, 20, {} }, + {INIT_DCS_CMD, 2, {0x85, 0x04} }, + {INIT_DCS_CMD, 2, {0x86, 0x08} }, + {INIT_DCS_CMD, 2, {0x83, 0xAA} }, + {INIT_DCS_CMD, 2, {0x84, 0x11} }, + {INIT_DCS_CMD, 2, {0x98, 0x12} }, + +}; + +struct panel_info krane_panel_info[] = { + PANEL(PANEL_KRANE_BOE_TV101WUM_NL2, + 74000, + kukui_boe_edid, + lcm_boe_init_cmd), + {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id krane_get_panel_id(struct board_display_intf *intf) +{ + return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL2; +}; + +static bool krane_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KRANE_UNKNOWN) + return true; + return false; +}; + + +static int krane_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int krane_power(struct board_display_intf *intf) +{ + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(1500); + //gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + mdelay(5); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + mdelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + } + + return 0; + +}; + +struct board_display_intf bitland_panel_display_intf = { + .board = "krane", + .all_panel_info = krane_panel_info, + .all_panel_info_size = ARRAY_SIZE(krane_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &krane_get_panel_id, + .is_panel_id_valid = &krane_is_panel_id_valid, + .backlight = &krane_backlight, + .power = &krane_power, +}; + -- To view, visit https://review.coreboot.org/c/coreboot/+/33184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1191b33c63ba9947e700670882a048b014fb7c27 Gerrit-Change-Number: 33184 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: riscv: add support to boot linux kernel binary using opensbi
by Xiang Wang (Code Review) 03 Aug '19

03 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32394 Change subject: riscv: add support to boot linux kernel binary using opensbi ...................................................................... riscv: add support to boot linux kernel binary using opensbi Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/Kconfig M payloads/external/Makefile.inc M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/soc/sifive/fu540/Kconfig 5 files changed, 49 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32394/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44..4cf9d1e 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -28,6 +28,18 @@ You will be able to specify the location and file name of the payload image later. +config PAYLOAD_RISCV_LINUX_BINARY + bool "An linux binary payload" + depends on ARCH_RISCV + help + Select this option if you have a payload image (an binary file) + which coreboot should run as soon as the basic hardware + initialization is completed. This image will be used as the + payload of opensbi and will be started by coreboot. + + You will be able to specify the location and file name of the + payload image later. + config PAYLOAD_FIT bool "A FIT payload" depends on ARCH_ARM64 @@ -57,9 +69,10 @@ config PAYLOAD_FILE string "Payload path and filename" - depends on PAYLOAD_ELF || PAYLOAD_FIT + depends on PAYLOAD_ELF || PAYLOAD_FIT || PAYLOAD_RISCV_LINUX_BINARY default "payload.elf" if PAYLOAD_ELF default "uImage" if PAYLOAD_FIT + default "payload.bin" if PAYLOAD_RISCV_LINUX_BINARY help The path and filename of the ELF executable file to use as payload. diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5f9d800..3b29b41 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -48,7 +48,11 @@ endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) +$(CONFIG_CBFS_PREFIX)/payload-file := $(obj)/opensbi.elf +else $(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) +endif ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) $(CONFIG_CBFS_PREFIX)/payload-type := flat-binary else diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d5f6295..d4d362b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -174,4 +174,27 @@ endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_RAMSTAGE_RISCV + +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) + +OPENSBI := $(obj)/opensbi.elf +OPENSBI_SOURCE := $(top)/payloads/external/opensbi +OPENSBI_BUILD := $(abspath $(obj)/payloads/external/opensbi) +OPENSBI_TARGET := $(OPENSBI_BUILD)/platform/$(CONFIG_OPENSBI_PLATFORM)/firmware/fw_payload.elf + +$(OPENSBI):$(obj)/build.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + mkdir -p $(OPENSBI_BUILD) + $(MAKE) \ + -C $(OPENSBI_SOURCE) \ + CROSS_COMPILE=riscv64-elf- \ + PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ + O=$(OPENSBI_BUILD) \ + FW_PAYLOAD_PATH=$(abspath $(CONFIG_PAYLOAD_FILE)) + cp $(OPENSBI_TARGET) $(abspath $@) + +.PHONY: $(OPENSBI) + +endif #CONFIG_PAYLOAD_RISCV_LINUX_BINARY + endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 535067e..9998255 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -49,7 +49,11 @@ fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { +#if CONFIG(PAYLOAD_RISCV_LINUX_BINARY) + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_M); +#else run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); +#endif return; } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..2e88150 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config OPENSBI_PLATFORM + string + default "sifive/fu540" + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Gerrit-Change-Number: 32394 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

5 27

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM
by Patrick Georgi (Code Review) 02 Aug '19

02 Aug '19

Hello nsekar(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32271 to review the following change. Change subject: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM ...................................................................... TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM This patch adds support to select the board id based on the TPM availability. Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/boardid.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32271/1 diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c index 8258ac3..9a0d309 100644 --- a/src/mainboard/google/mistral/boardid.c +++ b/src/mainboard/google/mistral/boardid.c @@ -32,7 +32,22 @@ [1] = GPIO(106), [0] = GPIO(105)}; - bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + if (is_tpm_detected() == 0) { + bid = 25; /* Assign 25 for EVB boards */ + printk(BIOS_DEBUG, "EVB Board ID: %d\n", bid); + } else { + bid = 0; /* Assign 0 for Proto boards */ + + /* The board id assigned for Proto boards is 0. + * Since gpios are not wired in the initial phase, + * we will get 0 whihch is a coincidence. + * To make sure it starts working, after gpios are + * wired, reassign the value read from gpios to id. + */ + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_DEBUG, "Proto Board ID: %d\n", bid); + } return bid; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Gerrit-Change-Number: 32271 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: mediatek: Refactor I2C code among similar SOCs
by wang qii (Code Review) 02 Aug '19

02 Aug '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30975 Change subject: mediatek: Refactor I2C code among similar SOCs ...................................................................... mediatek: Refactor I2C code among similar SOCs Refactor I2C code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Signed-off-by: qii wang <qii.wang(a)mediatek.com> --- A src/soc/mediatek/common/i2c.c A src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h 5 files changed, 390 insertions(+), 354 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30975/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c new file mode 100644 index 0000000..73414ac --- /dev/null +++ b/src/soc/mediatek/common/i2c.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <delay.h> +#include <timer.h> +#include <symbols.h> +#include <arch/io.h> +#include <soc/i2c.h> +#include <device/i2c_simple.h> + +static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs) +{ + write32(&dma_regs->dma_rst, 0x1); + udelay(50); + write32(&dma_regs->dma_rst, 0x2); + udelay(50); + write32(&dma_regs->dma_rst, 0x0); + udelay(50); +} + +static inline void mtk_i2c_dump_info(uint8_t bus) +{ + struct mt_i2c_regs *regs; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + + printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n" + "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n" + "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n" + "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n", + (read32(&regs->slave_addr)), + (read32(&regs->intr_mask)), + (read32(&regs->intr_stat)), + (read32(&regs->control)), + (read32(&regs->transfer_len)), + (read32(&regs->transac_len)), + (read32(&regs->delay_len)), + (read32(&regs->timing)), + (read32(&regs->start)), + (read32(&regs->fifo_stat)), + (read32(&regs->io_config)), + (read32(&regs->hs)), + (read32(&regs->debug_stat)), + (read32(&regs->ext_conf))); +} + +static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes read) +{ + uint32_t ret_code = I2C_OK; + uint16_t status; + uint32_t time_out_val = 0; + uint8_t addr; + uint32_t write_len = 0; + uint32_t read_len = 0; + uint8_t *write_buffer = NULL; + uint8_t *read_buffer = NULL; + struct mt_i2c_regs *regs; + struct mt_i2c_dma_regs *dma_regs; + struct stopwatch sw; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs; + + addr = seg[0].slave; + + switch (read) { + case I2C_WRITE_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + write_len = seg[0].len; + write_buffer = seg[0].buf; + break; + + case I2C_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + read_len = seg[0].len; + read_buffer = seg[0].buf; + break; + + /* Must use special write-then-read mode for repeated starts. */ + case I2C_WRITE_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + assert(seg[1].len > 0 && seg[1].len <= 255); + write_len = seg[0].len; + read_len = seg[1].len; + write_buffer = seg[0].buf; + read_buffer = seg[1].buf; + break; + } + + /* Clear interrupt status */ + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + write32(&regs->fifo_addr_clr, 0x1); + + /* Enable interrupt */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + switch (read) { + case I2C_WRITE_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, write_len); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + break; + + case I2C_READ_MODE: + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, read_len); + + /* set i2c read slave address*/ + write32(&regs->slave_addr, (addr << 1 | 0x1)); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + + case I2C_WRITE_READ_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + DIR_CHG | ACK_ERR_DET_EN | DMA_EN | + CLK_EXT | REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transfer_len, write_len); + write32(&regs->transfer_aux_len, read_len); + write32(&regs->transac_len, 2); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + } + + write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_en, I2C_DMA_START_EN); + + /* start transfer transaction */ + write32(&regs->start, 0x1); + + stopwatch_init_msecs_expire(&sw, 100); + + /* polling mode : see if transaction complete */ + while (1) { + status = read32(&regs->intr_stat); + if (status & I2C_HS_NACKERR) { + ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_ACKERR) { + ret_code = I2C_TRANSFER_FAIL_ACKERR; + printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_TRANSAC_COMP) { + ret_code = I2C_OK; + memcpy(read_buffer, _dma_coherent, read_len); + break; + } + + if (stopwatch_expired(&sw)) { + ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, + time_out_val); + mtk_i2c_dump_info(bus); + break; + } + } + + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + /* clear bit mask */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + /* reset the i2c controller for next i2c transfer. */ + write32(&regs->softreset, 0x1); + + i2c_dma_reset(dma_regs); + + return ret_code; +} + +static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) +{ + if (left_count >= 2 && + !(seg[0].flags & I2C_M_RD) && + (seg[1].flags & I2C_M_RD) && + seg[0].slave == seg[1].slave) + return 1; + else + return 0; +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + int ret = 0; + int i; + int read; + + for (i = 0; i < seg_count; i++) { + if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { + read = I2C_WRITE_READ_MODE; + } else { + read = (segments[i].flags & I2C_M_RD) ? + I2C_READ_MODE : I2C_WRITE_MODE; + } + + ret = mtk_i2c_transfer(bus, &segments[i], read); + + if (ret) + break; + + if (read == I2C_WRITE_READ_MODE) + i++; + } + + return ret; +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_init(bus); +} diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h new file mode 100755 index 0000000..e455f35 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_COMMON_I2C_H +#define MTK_COMMON_I2C_H + +/* I2C DMA Registers */ +struct mt_i2c_dma_regs { + uint32_t dma_int_flag; + uint32_t dma_int_en; + uint32_t dma_en; + uint32_t dma_rst; + uint32_t reserved1; + uint32_t dma_flush; + uint32_t dma_con; + uint32_t dma_tx_mem_addr; + uint32_t dma_rx_mem_addr; + uint32_t dma_tx_len; + uint32_t dma_rx_len; +}; + +check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); + +/* I2C Configuration */ +enum { + I2C_HS_DEFAULT_VALUE = 0x0102, +}; + +enum i2c_modes { + I2C_WRITE_MODE = 0, + I2C_READ_MODE = 1, + I2C_WRITE_READ_MODE = 2, +}; + +enum { + I2C_DMA_CON_TX = 0x0, + I2C_DMA_CON_RX = 0x1, + I2C_DMA_START_EN = 0x1, + I2C_DMA_INT_FLAG_NONE = 0x0, + I2C_DMA_CLR_FLAG = 0x0, + I2C_DMA_FLUSH_FLAG = 0x1, +}; + +enum { + I2C_TRANS_LEN_MASK = (0xff), + I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), + I2C_CONTROL_MASK = (0x3f << 1) +}; + +/* Register mask */ +enum { + I2C_HS_NACKERR = (1 << 2), + I2C_ACKERR = (1 << 1), + I2C_TRANSAC_COMP = (1 << 0), +}; + +/* i2c control bits */ +enum { + ASYNC_MODE = (1 << 9), + DMAACK_EN = (1 << 8), + ACK_ERR_DET_EN = (1 << 5), + DIR_CHG = (1 << 4), + CLK_EXT = (1 << 3), + DMA_EN = (1 << 2), + REPEATED_START_FLAG = (1 << 1), + STOP_FLAG = (0 << 1) +}; + +/* I2C Status Code */ + +enum { + I2C_OK = 0x0000, + I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, + I2C_TRANSFER_INVALID_LENGTH = 0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, + I2C_TRANSFER_FAIL_ACKERR = 0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 +}; + +struct mtk_i2c { + struct mt_i2c_regs *i2c_regs; + struct mt_i2c_dma_regs *i2c_dma_regs; +}; + +extern struct mtk_i2c mtk_i2c_bus_controller[]; + +void mtk_i2c_bus_init(uint8_t bus); +#endif diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b004c27..5a54d6d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -17,7 +17,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c -bootblock-y += i2c.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -32,7 +32,7 @@ ################################################################################ -verstage-y += i2c.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/spi.c spi.c verstage-y += ../common/uart.c @@ -49,7 +49,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c -romstage-y += i2c.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c @@ -71,7 +71,8 @@ ramstage-y += ../common/timer.c ramstage-y += timer.c ramstage-y += ../common/uart.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c +ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index b4c3aa9..85f676c 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -14,19 +14,13 @@ */ #include <assert.h> -#include <delay.h> -#include <device/i2c_simple.h> -#include <string.h> -#include <symbols.h> -#include <timer.h> #include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/i2c.h> #include <soc/pll.h> +#include <soc/i2c.h> #define I2C_CLK_HZ (AXI_HZ / 16) -static struct mtk_i2c i2c[7] = { +struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ { .i2c_regs = (void *)I2C_BASE, @@ -68,277 +62,21 @@ } }; -#define I2CTAG "[I2C][PL] " - -#if IS_ENABLED(CONFIG_DEBUG_I2C) -#define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) -#else -#define I2CLOG(fmt, arg...) -#endif /* CONFIG_DEBUG_I2C */ - -#define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg) - -static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) +void mtk_i2c_init(uint8_t bus) { - write32(&dma_regs->dma_rst, 0x1); - udelay(50); - write32(&dma_regs->dma_rst, 0x2); - udelay(50); - write32(&dma_regs->dma_rst, 0x0); - udelay(50); -} - -void mtk_i2c_bus_init(uint8_t bus) -{ - uint8_t sample_div; uint8_t step_div; uint32_t i2c_freq; + const uint8_t sample_div = 1; - assert(bus < ARRAY_SIZE(i2c)); + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); /* Calculate i2c frequency */ - sample_div = 1; step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); /* Init i2c bus Timing register */ - write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 | - (step_div - 1)); -} - -static inline void mtk_i2c_dump_info(uint8_t bus) -{ - struct mt8173_i2c_regs *regs; - - regs = i2c[bus].i2c_regs; - - I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" - "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" - "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" - "DEBUGSTAT %x\nEXT_CONF %x\n", - (read32(&regs->salve_addr)), - (read32(&regs->intr_mask)), - (read32(&regs->intr_stat)), - (read32(&regs->control)), - (read32(&regs->transfer_len)), - (read32(&regs->transac_len)), - (read32(&regs->delay_len)), - (read32(&regs->timing)), - (read32(&regs->start)), - (read32(&regs->fifo_stat)), - (read32(&regs->io_config)), - (read32(&regs->hs)), - (read32(&regs->debug_stat)), - (read32(&regs->ext_conf))); - - I2CLOG("addr address %x\n", (uint32_t)regs); -} - -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes read) -{ - uint32_t ret_code = I2C_OK; - uint16_t status; - uint32_t time_out_val = 0; - uint8_t addr; - uint32_t write_len = 0; - uint32_t read_len = 0; - uint8_t *write_buffer = NULL; - uint8_t *read_buffer = NULL; - struct mt8173_i2c_regs *regs; - struct mt8173_i2c_dma_regs *dma_regs; - struct stopwatch sw; - - regs = i2c[bus].i2c_regs; - dma_regs = i2c[bus].i2c_dma_regs; - - addr = seg[0].slave; - - switch (read) { - case I2C_WRITE_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - write_len = seg[0].len; - write_buffer = seg[0].buf; - break; - - case I2C_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - read_len = seg[0].len; - read_buffer = seg[0].buf; - break; - - /* Must use special write-then-read mode for repeated starts. */ - case I2C_WRITE_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - assert(seg[1].len > 0 && seg[1].len <= 255); - write_len = seg[0].len; - read_len = seg[1].len; - write_buffer = seg[0].buf; - read_buffer = seg[1].buf; - break; - } - - /* Clear interrupt status */ - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - write32(&regs->fifo_addr_clr, 0x1); - - /* Enable interrupt */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - switch (read) { - case I2C_WRITE_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, write_len); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - break; - - case I2C_READ_MODE: - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, read_len); - - /* set i2c read slave address*/ - write32(&regs->slave_addr, (addr << 1 | 0x1)); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - - case I2C_WRITE_READ_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN | - CLK_EXT | REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transfer_len, write_len); - write32(&regs->transfer_aux_len, read_len); - write32(&regs->transac_len, 2); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - } - - write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_en, I2C_DMA_START_EN); - - /* start transfer transaction */ - write32(&regs->start, 0x1); - - stopwatch_init_msecs_expire(&sw, 100); - - /* polling mode : see if transaction complete */ - while (1) { - status = read32(&regs->intr_stat); - if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; - I2CERR("[i2c%d transfer] transaction NACK error\n", - bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; - I2CERR("[i2c%d transfer] transaction ACK error\n", bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; - memcpy(read_buffer, _dma_coherent, read_len); - break; - } - - if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; - I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus, - time_out_val); - mtk_i2c_dump_info(bus); - break; - } - } - - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - /* clear bit mask */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - /* reset the i2c controller for next i2c transfer. */ - write32(&regs->softreset, 0x1); - - i2c_dma_reset(dma_regs); - - return ret_code; -} - -static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) -{ - if (left_count >= 2 && - !(seg[0].flags & I2C_M_RD) && - (seg[1].flags & I2C_M_RD) && - seg[0].slave == seg[1].slave) - return 1; - else - return 0; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, - int seg_count) -{ - int ret = 0; - int i; - int read; - - for (i = 0; i < seg_count; i++) { - if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { - read = I2C_WRITE_READ_MODE; - } else { - read = (segments[i].flags & I2C_M_RD) ? - I2C_READ_MODE : I2C_WRITE_MODE; - } - - ret = mtk_i2c_transfer(bus, &segments[i], read); - - if (ret) - break; - - if (read == I2C_WRITE_READ_MODE) - i++; - } - - return ret; + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); } diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h old mode 100644 new mode 100755 index 5f46e9c..f2f9cf2 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -16,47 +16,10 @@ #ifndef SOC_MEDIATEK_MT8173_I2C_H #define SOC_MEDIATEK_MT8173_I2C_H -#include <stddef.h> - -/* I2C Configuration */ -enum { - I2C_HS_DEFAULT_VALUE = 0x0102, -}; - -enum i2c_modes { - I2C_WRITE_MODE = 0, - I2C_READ_MODE = 1, - I2C_WRITE_READ_MODE = 2, -}; - -enum { - I2C_DMA_CON_TX = 0x0, - I2C_DMA_CON_RX = 0x1, - I2C_DMA_START_EN = 0x1, - I2C_DMA_INT_FLAG_NONE = 0x0, - I2C_DMA_CLR_FLAG = 0x0, - I2C_DMA_FLUSH_FLAG = 0x1, -}; - -/* I2C DMA Registers */ -struct mt8173_i2c_dma_regs { - uint32_t dma_int_flag; - uint32_t dma_int_en; - uint32_t dma_en; - uint32_t dma_rst; - uint32_t reserved1; - uint32_t dma_flush; - uint32_t dma_con; - uint32_t dma_tx_mem_addr; - uint32_t dma_rx_mem_addr; - uint32_t dma_tx_len; - uint32_t dma_rx_len; -}; - -check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24); +#include <soc/i2c_common.h> /* I2C Register */ -struct mt8173_i2c_regs { +struct mt_i2c_regs { uint32_t data_port; uint32_t slave_addr; uint32_t intr_mask; @@ -85,48 +48,8 @@ uint32_t transfer_aux_len; }; -check_member(mt8173_i2c_regs, debug_stat, 0x64); +check_member(mt_i2c_regs, debug_stat, 0x64); -struct mtk_i2c { - struct mt8173_i2c_regs *i2c_regs; - struct mt8173_i2c_dma_regs *i2c_dma_regs; -}; - -enum { - I2C_TRANS_LEN_MASK = (0xff), - I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), - I2C_CONTROL_MASK = (0x3f << 1) -}; - -/* Register mask */ -enum { - I2C_HS_NACKERR = (1 << 2), - I2C_ACKERR = (1 << 1), - I2C_TRANSAC_COMP = (1 << 0), -}; - -/* i2c control bits */ -enum { - ACK_ERR_DET_EN = (1 << 5), - DIR_CHG = (1 << 4), - CLK_EXT = (1 << 3), - DMA_EN = (1 << 2), - REPEATED_START_FLAG = (1 << 1), - STOP_FLAG = (0 << 1) -}; - -/* I2C Status Code */ - -enum { - I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 -}; - -void mtk_i2c_bus_init(uint8_t bus); +void mtk_i2c_init(uint8_t bus); #endif /* SOC_MEDIATEK_MT8173_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Gerrit-Change-Number: 30975 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned
by Xiang Wang (Code Review) 02 Aug '19

02 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31383 Change subject: lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned ...................................................................... lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned They were sized to 32-bit algnment, this grows them to 64 bit-aligned Change-Id: Id401ed7ac24d781329686cf0a339cf9e1ea15130 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/lib/coreboot_table.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31383/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index c2ae094..25d0afa 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -422,7 +422,7 @@ struct lb_timestamp *rec; rec = (struct lb_timestamp *)lb_new_record(header); rec->tag = LB_TAG_VERSION_TIMESTAMP; - rec->size = sizeof(*rec); + rec->size = ALIGN_UP(sizeof(*rec), 8); rec->timestamp = coreboot_version_timestamp; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id401ed7ac24d781329686cf0a339cf9e1ea15130 Gerrit-Change-Number: 31383 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: fu540: add code to initialize flash
by Xiang Wang (Code Review) 02 Aug '19

02 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466 Change subject: fu540: add code to initialize flash ...................................................................... fu540: add code to initialize flash SiFive's ZSBL has initialized flash, but only 16MB of space is available. I fixed it to use all 32MB. Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/flash.c M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/spi.h A src/soc/sifive/fu540/include/soc/spi_flash.h A src/soc/sifive/fu540/spi.c 8 files changed, 506 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 27ddcba..2dac283 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,6 +11,10 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += flash.c +bootblock-y += bootblock.c + +romstage-y += flash.c romstage-y += romstage.c bootblock-y += memlayout.ld diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c new file mode 100644 index 0000000..777b2aa --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); +extern void bootblock_mainboard_init(void); + +void bootblock_mainboard_init(void) +{ + flash_init(); +} diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c new file mode 100644 index 0000000..a29ac24 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/flash.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); + +const static spi_reg_ffmt ffmt= { + .cmd_en = 1, + .addr_len = 4, + .pad_cnt = 8, + .command_proto = SPI_PROTO_S, + .addr_proto = SPI_PROTO_S, + .data_proto = SPI_PROTO_Q, + .command_code = 0x6c +}; + + +void flash_init(void) +{ + initialize_spi_flash_mmap_quad( + (spi_ctrl*)FU540_QSPI0, + clock_get_tlclk_khz(), + ffmt.raw_bits, + 0x66, + 0x99); +} diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 8277141..1675aca 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -21,6 +21,8 @@ #include <soc/clock.h> #include <soc/sdram.h> +extern void flash_init(void); + void main(void) { console_init(); @@ -39,6 +41,7 @@ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) uart_init(CONFIG_UART_FOR_CONSOLE); + flash_init(); sdram_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 4f62f3e..83c7b1c 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c +bootblock-y += spi.c romstage-y += uart.c romstage-y += clint.c @@ -26,6 +27,7 @@ romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c +romstage-y += spi.c ramstage-y += uart.c ramstage-y += clint.c @@ -34,6 +36,7 @@ ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c +ramstage-y += spi.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h new file mode 100644 index 0000000..c40ae7c --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_H__ + +#include <stdint.h> + +#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide") + +typedef union +{ + struct + { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_sckmode; +_ASSERT_SIZEOF(spi_reg_sckmode, 4); + + +typedef union +{ + struct + { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_csmode; +_ASSERT_SIZEOF(spi_reg_csmode, 4); + + +typedef union +{ + struct + { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay0; +_ASSERT_SIZEOF(spi_reg_delay0, 4); + + +typedef union +{ + struct + { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay1; +_ASSERT_SIZEOF(spi_reg_delay1, 4); + + +typedef union +{ + struct + { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +} spi_reg_fmt; +_ASSERT_SIZEOF(spi_reg_fmt, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +} spi_reg_txdata; +_ASSERT_SIZEOF(spi_reg_txdata, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +} spi_reg_rxdata; +_ASSERT_SIZEOF(spi_reg_rxdata, 4); + + +typedef union +{ + struct + { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_txmark; +_ASSERT_SIZEOF(spi_reg_txmark, 4); + + +typedef union +{ + struct + { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_rxmark; +_ASSERT_SIZEOF(spi_reg_rxmark, 4); + + +typedef union +{ + struct + { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +} spi_reg_fctrl; +_ASSERT_SIZEOF(spi_reg_fctrl, 4); + + +typedef union +{ + struct + { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t command_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t command_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +} spi_reg_ffmt; +_ASSERT_SIZEOF(spi_reg_ffmt, 4); + + +typedef union +{ + struct + { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_ie; +typedef spi_reg_ie spi_reg_ip; +_ASSERT_SIZEOF(spi_reg_ie, 4); +_ASSERT_SIZEOF(spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +typedef volatile struct +{ + uint32_t sckdiv; + spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + spi_reg_delay0 delay0; + spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + spi_reg_fmt fmt; + uint32_t reserved44; + spi_reg_txdata txdata; + spi_reg_rxdata rxdata; + + spi_reg_txmark txmark; + spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + spi_reg_ie ie; + spi_reg_ip ip; +} spi_ctrl; + + +void spi_tx(spi_ctrl* spictrl, uint8_t in); +uint8_t spi_rx(spi_ctrl* spictrl); +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in); + +// Inlining header functions in C +// https://stackoverflow.com/a/23699777/7433423 + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not exceed + // max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed + // 2^32 - 1, which is unlikely since we represent frequencies in kHz. + unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */ diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h new file mode 100644 index 0000000..9926b82 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi_flash.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ + +#include <soc/spi.h> +#include <stdint.h> + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +/** + * Set up SPI for direct, non-memory-mapped access. + */ + +static inline int initialize_spi_flash_direct( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + return 0; +} + +static inline int _initialize_spi_flash_mmap( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + spictrl->ffmt.raw_bits = ffmt_rawbits; + + spictrl->fctrl.en = 1; + __asm__ __volatile__ ("fence io, io"); + return 0; +} + + +static inline int initialize_spi_flash_mmap_single( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + + +static inline int initialize_spi_flash_mmap_quad( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */ + diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c new file mode 100644 index 0000000..01a58dd --- /dev/null +++ b/src/soc/sifive/fu540/spi.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/spi.h> + +/** + * Wait until SPI is ready for transmission and transmit byte. + */ +void spi_tx(spi_ctrl* spictrl, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl->txdata.raw_bits < 0); + spictrl->txdata.data = in; +#endif +} + + +/** + * Wait until SPI receive queue has data and read byte. + */ +uint8_t spi_rx(spi_ctrl* spictrl) +{ + int32_t out; + while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0); + return (uint8_t) out; +} + + +/** + * Transmit a byte and receive a byte. + */ +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in) +{ + spi_tx(spictrl, in); + return spi_rx(spictrl); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/30466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Gerrit-Change-Number: 30466 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

6 50

Change in ...coreboot[master]: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC
by Richard Spiegel (Code Review) 31 Jul '19

31 Jul '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33624 Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC ...................................................................... soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC Merlinfalcon is essentially a carrizo CPU in a SOC presentation. Just as stoneyridge, they are both family 15h CPU, thus most of the code is similar if not identical. Add changes base on config parameter SOC_AMD_MERLINFALCON_FP4 to accommodate for merlinfalcon SOC. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 61 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/33624/1 diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index d1a7d30..6eb2ec7 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -20,12 +20,18 @@ #include <stdint.h> #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <soc/cpu.h> #include <soc/i2c.h> #include <arch/acpi_device.h> #define MAX_NODES 1 +#if CONFIG(SOC_AMD_MERLINFALCON_FP4) +#define MAX_DRAM_CH 2 +#define MAX_DIMMS_PER_CH 4 +#else #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#endif #define STONEY_I2C_DEV_MAX 4 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..f751dc8 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -145,6 +145,7 @@ }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x660f01 }, { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, }; diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 02fed7a..01a0b7c 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -39,17 +39,24 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* Internal Graphics */ +/* + * Internal Graphics + * Device IDs subject to SKU/OPN variation + * GFX_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX + * GFX_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX + */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) -/* HD Audio 0 */ +/* HD Audio 0 + * Device IDs + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA + */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) @@ -109,45 +116,63 @@ #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) -/* HT Configuration */ +/* HT Configuration + * Device IDs + * HT_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT + * HT_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT + */ #define HT_DEV 0x18 #define HT_FUNC 0 -#define HT_DEVID 0x15b0 #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) #define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) -/* Address Maps */ +/* Address Maps + * Device IDs + * ADDR_DEVID for merlinfalcon 0x1571 + * ADDR_DEVID for stoneyridge 0x15b1 + */ #define ADDR_DEV 0x18 #define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) #define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) -/* DRAM Configuration */ +/* DRAM Configuration + * Device IDs + * DCT_DEVID for merlinfalcon 0x1572 + * DCT_DEVID for stoneyridge 0x15b2 + */ #define DCT_DEV 0x18 #define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) #define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) -/* Misc. Configuration */ +/* Misc. Configuration + * Device IDs + * MISC_DEVID for merlinfalcon 0x1573 + * MISC_DEVID for stoneyridge 0x15b3 + */ #define MISC_DEV 0x18 #define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) #define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) -/* PM Configuration */ +/* PM Configuration + * Device IDs + * PM_DEVID for merlinfalcon 0x1574 + * PM_DEVID for stoneyridge 0x15b4 + */ #define PM_DEV 0x18 #define PM_FUNC 4 -#define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -/* Northbridge Configuration */ +/* Northbridge Configuration + * Device IDs + * NB_DEVID for merlinfalcon 0x1575 + * NB_DEVID for stoneyridge 0x15b5 + */ #define NB_DEV 0x18 #define NB_FUNC 5 -#define NB_DEVID 0x15b5 #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 5985832..7284f23 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -347,10 +347,15 @@ .ops_pci = 0, }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, + PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + 0 }; + static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + .devices = pci_device_ids, }; /* @@ -464,9 +469,13 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; + + if ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) + new_vendev = 0x100298e0; + else if ((vendev >= 0x10029870) && (vendev <= 0x1002987f)) + new_vendev = 0x10029870; + else + new_vendev = vendev; if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/33624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Gerrit-Change-Number: 33624 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 29

Change in ...coreboot[master]: mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 ...
by Sumeet R Pawnikar (Code Review) 31 Jul '19

31 Jul '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33147 Change subject: mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 degree C ...................................................................... mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 degree C PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFA on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33147/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9d10cac..e5f4651 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,9 @@ # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms -- To view, visit https://review.coreboot.org/c/coreboot/+/33147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Gerrit-Change-Number: 33147 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

9 41

Change in ...coreboot[master]: google/kukui: Enable config for coreboot display
by yongqiang niu (Code Review) 31 Jul '19

31 Jul '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31521 Change subject: google/kukui: Enable config for coreboot display ...................................................................... google/kukui: Enable config for coreboot display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31521/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..9d2634a 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -37,6 +37,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Gerrit-Change-Number: 31521 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: soc/ucb/riscv: Protect CBFS from payload loader
by Patrick Rudolph (Code Review) 30 Jul '19

30 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33426 Change subject: soc/ucb/riscv: Protect CBFS from payload loader ...................................................................... soc/ucb/riscv: Protect CBFS from payload loader The payload loader doesn't know about CBFS in DRAM. Mark the region as RAMSTAGE to make sure the payload won't overwrite the CBFS while decompressing. Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/ucb/riscv/Makefile.inc A src/soc/ucb/riscv/tables.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/33426/1 diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642..ba2a246 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -7,5 +7,6 @@ ramstage-y += cbmem.c ramstage-y += ipi.c +ramstage-y += tables.c endif diff --git a/src/soc/ucb/riscv/tables.c b/src/soc/ucb/riscv/tables.c new file mode 100644 index 0000000..749cb0c --- /dev/null +++ b/src/soc/ucb/riscv/tables.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootmem.h> + +void bootmem_platform_add_ranges(void) +{ + // Protect CBFS in DRAM + bootmem_add_range((uintptr_t)0x80000000, + CONFIG_COREBOOT_ROMSIZE_KB * 1024, BM_MEM_RAMSTAGE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1 Gerrit-Change-Number: 33426 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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