coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/soc/amd/picasso: Update GPIO configuration
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33761 Change subject: src/soc/amd/picasso: Update GPIO configuration ...................................................................... src/soc/amd/picasso: Update GPIO configuration Make the definitions match Picasso's definitions. Add/remove pins that differ from stoneyridge, update GEVENTs for the FCH mapping. Change-Id: I59f958151f27ed4ca0eb1a87ade6102eec1e5061 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/gpio.c M src/soc/amd/picasso/include/soc/gpio.h 2 files changed, 119 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33761/1 diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index f63a0d9..f8e698b 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -31,10 +31,6 @@ { GPIO_7, GEVENT_11 }, { GPIO_8, GEVENT_23 }, { GPIO_9, GEVENT_22 }, - { GPIO_11, GEVENT_18 }, - { GPIO_13, GEVENT_21 }, - { GPIO_14, GEVENT_6 }, - { GPIO_15, GEVENT_20 }, { GPIO_16, GEVENT_12 }, { GPIO_17, GEVENT_13 }, { GPIO_18, GEVENT_14 }, @@ -42,10 +38,13 @@ { GPIO_22, GEVENT_3 }, { GPIO_23, GEVENT_16 }, { GPIO_24, GEVENT_15 }, - { GPIO_65, GEVENT_0 }, - { GPIO_66, GEVENT_1 }, - { GPIO_68, GEVENT_9 }, - { GPIO_69, GEVENT_17 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, }; void soc_route_sci(uint8_t event) diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 411144b..bf034c3 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -43,7 +43,6 @@ #define GPIO_12 12 #define GPIO_13 13 #define GPIO_14 14 -#define GPIO_15 15 #define GPIO_16 16 #define GPIO_17 17 #define GPIO_18 18 @@ -53,22 +52,20 @@ #define GPIO_22 22 #define GPIO_23 23 #define GPIO_24 24 -#define GPIO_25 25 #define GPIO_26 26 -#define GPIO_39 39 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 #define GPIO_40 40 #define GPIO_42 42 /* Bank 1: GPIO_64 - GPIO_127 */ -#define GPIO_64 64 -#define GPIO_65 65 -#define GPIO_66 66 #define GPIO_67 67 #define GPIO_68 68 #define GPIO_69 69 #define GPIO_70 70 -#define GPIO_71 71 -#define GPIO_72 72 #define GPIO_74 74 #define GPIO_75 75 #define GPIO_76 76 @@ -81,34 +78,25 @@ #define GPIO_90 90 #define GPIO_91 91 #define GPIO_92 92 -#define GPIO_93 93 -#define GPIO_95 95 -#define GPIO_96 96 -#define GPIO_97 97 -#define GPIO_98 98 -#define GPIO_99 99 -#define GPIO_100 100 -#define GPIO_101 101 -#define GPIO_102 102 +#define GPIO_103 103 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 #define GPIO_113 113 #define GPIO_114 114 #define GPIO_115 115 #define GPIO_116 116 -#define GPIO_117 117 -#define GPIO_118 118 -#define GPIO_119 119 #define GPIO_120 120 #define GPIO_121 121 -#define GPIO_122 122 -#define GPIO_126 126 /* Bank 2: GPIO_128 - GPIO_183 */ #define GPIO_129 129 #define GPIO_130 130 #define GPIO_131 131 #define GPIO_132 132 -#define GPIO_133 133 -#define GPIO_134 134 #define GPIO_135 135 #define GPIO_136 136 #define GPIO_137 137 @@ -119,15 +107,11 @@ #define GPIO_142 142 #define GPIO_143 143 #define GPIO_144 144 -#define GPIO_145 145 -#define GPIO_146 146 -#define GPIO_147 147 -#define GPIO_148 148 #define GPIO_SCL_HIGH 0 #define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE -/* IOMUX function names and values generated from BKDG. */ +/* IOMUX function names and values generated from PPR. */ #define GPIO_0_IOMUX_PWR_BTN_L 0 #define GPIO_0_IOMUX_GPIOxx 1 #define GPIO_1_IOMUX_SYS_RESET_L 0 @@ -139,35 +123,32 @@ #define GPIO_5_IOMUX_GPIOxx 0 #define GPIO_5_IOMUX_DEVSLP0_S5 1 #define GPIO_6_IOMUX_GPIOxx 0 -#define GPIO_6_IOMUX_LDT_RST_L 1 +#define GPIO_6_IOMUX_DEVSLP1_S5 1 #define GPIO_7_IOMUX_GPIOxx 0 -#define GPIO_7_IOMUX_LDT_PWROK 1 +#define GPIO_7_IOMUX_ACP_I2S_SDIN 1 #define GPIO_8_IOMUX_GPIOxx 0 -#define GPIO_8_IOMUX_SerPortTX_OUT 1 +#define GPIO_8_IOMUX_ACP_I2S_LRCLK 1 #define GPIO_9_IOMUX_GPIOxx 0 -#define GPIO_9_IOMUX_SerPortRX_OUT 1 -#define GPIO_10_IOMUX_S0A3_GPIO 0 -#define GPIO_10_IOMUX_GPIOxx 1 +#define GPIO_9_IOMUX_SGPIO_DATAOUT 1 +#define GPIO_9_IOMUX_MDIO1_SCL 2 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3_GPIO 1 +#define GPIO_10_IOMUX_SGPIO_CLK 2 +#define GPIO_10_IOMUX_MDIO0_SCL 3 #define GPIO_11_IOMUX_GPIOxx 0 -#define GPIO_11_IOMUX_USB_OC7_L 1 -#define GPIO_12_IOMUX_IR_LED_L 0 -#define GPIO_12_IOMUX_LLB_L 1 -#define GPIO_12_IOMUX_GPIOxx 2 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 #define GPIO_13_IOMUX_USB_OC5_L 0 #define GPIO_13_IOMUX_GPIOxx 1 -#define GPIO_14_IOMUX_USB_OC6_L 0 +#define GPIO_14_IOMUX_USB_OC4_L 0 #define GPIO_14_IOMUX_GPIOxx 1 -#define GPIO_15_IOMUX_IR_RX1 0 -#define GPIO_15_IOMUX_GPIOxx 1 #define GPIO_16_IOMUX_USB_OC0_L 0 -#define GPIO_16_IOMUX_TRST_L 1 -#define GPIO_16_IOMUX_GPIOxx 2 +#define GPIO_16_IOMUX_GPIOxx 1 #define GPIO_17_IOMUX_USB_OC1_L 0 -#define GPIO_17_IOMUX_TDI 1 -#define GPIO_17_IOMUX_GPIOxx 2 +#define GPIO_17_IOMUX_GPIOxx 1 #define GPIO_18_IOMUX_USB_OC2_L 0 -#define GPIO_18_IOMUX_TCK 1 -#define GPIO_18_IOMUX_GPIOxx 2 +#define GPIO_18_IOMUX_GPIOxx 1 #define GPIO_19_IOMUX_SCL1 0 #define GPIO_19_IOMUX_I2C3_SCL 1 #define GPIO_19_IOMUX_GPIOxx 2 @@ -175,66 +156,107 @@ #define GPIO_20_IOMUX_I2C3_SDA 1 #define GPIO_20_IOMUX_GPIOxx 2 #define GPIO_21_IOMUX_LPC_PD_L 0 -#define GPIO_21_IOMUX_GPIOxx 1 +#define GPIO_21_IOMUX_EMMC_CMD 1 +#define GPIO_21_IOMUX_GPIOxx 2 #define GPIO_22_IOMUX_LPC_PME_L 0 -#define GPIO_22_IOMUX_GPIOxx 1 -#define GPIO_23_IOMUX_USB_OC4_L 0 -#define GPIO_23_IOMUX_IR_RX0 1 -#define GPIO_23_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 +#define GPIO_22_IOMUX_GPIOxx 2 +#define GPIO_23_IOMUX_ACP_PRES 0 +#define GPIO_23_IOMUX_SGPIO_LOAD 1 +#define GPIO_23_IOMUX_MDIO1_SDA 2 +#define GPIO_23_IOMUX_GPIOxx 3 #define GPIO_24_IOMUX_USB_OC3_L 0 #define GPIO_24_IOMUX_GPIOxx 1 -#define GPIO_25_IOMUX_SD0_CD 0 -#define GPIO_25_IOMUX_GPIOxx 1 #define GPIO_26_IOMUX_PCIE_RST_L 0 #define GPIO_26_IOMUX_GPIOxx 1 -#define GPIO_39_IOMUX_VDDGFX_PD 0 -#define GPIO_39_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_29_IOMUX_USB_OC6_L 2 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_ESPI_CS_L 1 +#define GPIO_31_IOMUX_GPIOxx 2 +#define GPIO_32_IOMUX_LPC_RST_L 0 +#define GPIO_32_IOMUX_SD_WP_L 1 +#define GPIO_32_IOMUX_GPIOxx 2 #define GPIO_40_IOMUX_GPIOxx 0 -#define GPIO_42_IOMUX_S5_MUX_CTRL 0 -#define GPIO_42_IOMUX_GPIOxx 1 -#define GPIO_64_IOMUX_GPIOxx 0 -#define GPIO_65_IOMUX_GPIOxx 0 -#define GPIO_66_IOMUX_GPIOxx 0 -#define GPIO_67_IOMUX_GPIOxx 0 -#define GPIO_67_IOMUX_DEVSLP0 1 +#define GPIO_40_IOMUX_SGPIO_DATAIN 1 +#define GPIO_40_IOMUX_MDIO0_SDA 2 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_68_IOMUX_EMMC_CD 1 #define GPIO_69_IOMUX_GPIOxx 0 -#define GPIO_69_IOMUX_SGPIO_LOAD 1 #define GPIO_70_IOMUX_GPIOxx 0 -#define GPIO_70_IOMUX_DEVSLP1 1 +#define GPIO_70_IOMUX_EMMC_CLK 1 +#define GPIO_70_IOMUX_SD_CLK 2 #define GPIO_74_IOMUX_LPCCLK0 0 -#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_EMMC_DATA4 1 +#define GPIO_74_IOMUX_GPIOxx 2 #define GPIO_75_IOMUX_LPCCLK1 0 -#define GPIO_75_IOMUX_GPIOxx 1 -#define GPIO_76_IOMUX_GPIOxx 0 -#define GPIO_76_IOMUX_SPI_TPM_CS_L 1 +#define GPIO_75_IOMUX_EMMC_DATA6 1 +#define GPIO_75_IOMUX_GPIOxx 2 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 #define GPIO_84_IOMUX_FANIN0 0 #define GPIO_84_IOMUX_GPIOxx 1 #define GPIO_85_IOMUX_FANOUT0 0 #define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_LPC_SMI_L 0 #define GPIO_86_IOMUX_GPIOxx 1 #define GPIO_87_IOMUX_SERIRQ 0 -#define GPIO_87_IOMUX_GPIOxx 1 +#define GPIO_87_IOMUX_EMMC_DATA7 1 +#define GPIO_87_IOMUX_GPIOxx 2 #define GPIO_88_IOMUX_LPC_CLKRUN_L 0 -#define GPIO_88_IOMUX_GPIOxx 1 -#define GPIO_90_IOMUX_GPIOxx 0 +#define GPIO_88_IOMUX_EMMC_DATA5 1 +#define GPIO_88_IOMUX_GPIOxx 2 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 #define GPIO_91_IOMUX_SPKR 0 #define GPIO_91_IOMUX_GPIOxx 1 #define GPIO_92_IOMUX_CLK_REQ0_L 0 #define GPIO_92_IOMUX_SATA_IS0_L 1 #define GPIO_92_IOMUX_SATA_ZP0_L 2 #define GPIO_92_IOMUX_GPIOxx 3 -#define GPIO_93_IOMUX_SD0_LED 0 -#define GPIO_93_IOMUX_GPIOxx 1 #define GPIO_95_IOMUX_GPIOxx 0 +#define GPIO_95_IOMUX_SD0_CLK 1 #define GPIO_96_IOMUX_GPIOxx 0 +#define GPIO_96_IOMUX_SD0_CMD 1 #define GPIO_97_IOMUX_GPIOxx 0 +#define GPIO_97_IOMUX_SD0_DATA0 1 #define GPIO_98_IOMUX_GPIOxx 0 +#define GPIO_98_IOMUX_SD0_DATA1 1 #define GPIO_99_IOMUX_GPIOxx 0 +#define GPIO_99_IOMUX_SD0_DATA2 1 #define GPIO_100_IOMUX_GPIOxx 0 -#define GPIO_101_IOMUX_SD0_WP 0 -#define GPIO_101_IOMUX_GPIOxx 1 -#define GPIO_102_IOMUX_SD0_PWR_CTRL 0 -#define GPIO_102_IOMUX_GPIOxx 1 +#define GPIO_100_IOMUX_SD0_DATA3 1 +#define GPIO_104_IOMUX_LAD0 0 +#define GPIO_104_IOMUX_EMMC_SDATA0 1 +#define GPIO_104_IOMUX_GPIOxx 3 +#define GPIO_105_IOMUX_LAD1 0 +#define GPIO_105_IOMUX_EMMC_DATA1 1 +#define GPIO_105_IOMUX_GPIOxx 3 +#define GPIO_106_IOMUX_LAD2 0 +#define GPIO_106_IOMUX_EMMC_DATA2 1 +#define GPIO_106_IOMUX_GPIOxx 3 +#define GPIO_107_IOMUX_LAD3 0 +#define GPIO_107_IOMUX_EMMC_DATA3 1 +#define GPIO_107_IOMUX_GPIOxx 3 +#define GPIO_108_IOMUX_LDRQ0_L 0 +#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_GPIOxx 2 +#define GPIO_109_IOMUX_LFRAME_L 0 +#define GPIO_109_IOMUX_EMMC_DS 1 +#define GPIO_109_IOMUX_GPIOxx 2 #define GPIO_113_IOMUX_SCL0 0 #define GPIO_113_IOMUX_I2C2_SCL 1 #define GPIO_113_IOMUX_GPIOxx 2 @@ -245,21 +267,10 @@ #define GPIO_115_IOMUX_GPIOxx 1 #define GPIO_116_IOMUX_CLK_REQ2_L 0 #define GPIO_116_IOMUX_GPIOxx 1 -#define GPIO_117_IOMUX_ESPI_CLK 0 -#define GPIO_117_IOMUX_GPIOxx 1 -#define GPIO_118_IOMUX_SPI_CS1_L 0 -#define GPIO_118_IOMUX_GPIOxx 1 -#define GPIO_119_IOMUX_SPI_CS2_L 0 -#define GPIO_119_IOMUX_ESPI_CS_L 1 -#define GPIO_119_IOMUX_GPIOxx 2 -#define GPIO_120_IOMUX_ESPI_DAT1 0 +#define GPIO_120_IOMUX_CLK_REQ5_L 0 #define GPIO_120_IOMUX_GPIOxx 1 -#define GPIO_121_IOMUX_ESPI_DAT0 0 +#define GPIO_121_IOMUX_CLK_REQ6_L 0 #define GPIO_121_IOMUX_GPIOxx 1 -#define GPIO_122_IOMUX_ESPI_DAT2 0 -#define GPIO_122_IOMUX_GPIOxx 1 -#define GPIO_126_IOMUX_GA20IN 0 -#define GPIO_126_IOMUX_GPIOxx 1 #define GPIO_129_IOMUX_KBRST_L 0 #define GPIO_129_IOMUX_GPIOxx 1 #define GPIO_130_IOMUX_SATA_ACT_L 0 @@ -268,39 +279,33 @@ #define GPIO_131_IOMUX_SATA_IS1_L 1 #define GPIO_131_IOMUX_SATA_ZP1_L 2 #define GPIO_131_IOMUX_GPIOxx 3 -#define GPIO_132_IOMUX_CLK_REQG_L 0 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 #define GPIO_132_IOMUX_OSCIN 1 #define GPIO_132_IOMUX_GPIOxx 2 -#define GPIO_133_IOMUX_ESPI_DAT3 0 -#define GPIO_133_IOMUX_GPIOxx 1 #define GPIO_135_IOMUX_UART0_CTS_L 0 -#define GPIO_135_IOMUX_GPIOxx 1 +#define GPIO_135_IOMUX_UART2_RXD 1 +#define GPIO_135_IOMUX_GPIOxx 2 #define GPIO_136_IOMUX_UART0_RXD 0 #define GPIO_136_IOMUX_GPIOxx 1 #define GPIO_137_IOMUX_UART0_RTS_L 0 -#define GPIO_137_IOMUX_GPIOxx 1 +#define GPIO_137_IOMUX_UART2_TXD 1 +#define GPIO_137_IOMUX_GPIOxx 2 #define GPIO_138_IOMUX_UART0_TXD 0 #define GPIO_138_IOMUX_GPIOxx 1 #define GPIO_139_IOMUX_UART0_INTR 0 #define GPIO_139_IOMUX_GPIOxx 1 #define GPIO_140_IOMUX_UART1_CTS_L 0 -#define GPIO_140_IOMUX_GPIOxx 1 +#define GPIO_140_IOMUX_UART3_TXD 1 +#define GPIO_140_IOMUX_GPIOxx 2 #define GPIO_141_IOMUX_UART1_RXD 0 #define GPIO_141_IOMUX_GPIOxx 1 #define GPIO_142_IOMUX_UART1_RTS_L 0 -#define GPIO_142_IOMUX_GPIOxx 1 +#define GPIO_142_IOMUX_UART3_RXD 1 +#define GPIO_142_IOMUX_GPIOxx 2 #define GPIO_143_IOMUX_UART1_TXD 0 #define GPIO_143_IOMUX_GPIOxx 1 #define GPIO_144_IOMUX_UART1_INTR 0 #define GPIO_144_IOMUX_GPIOxx 1 -#define GPIO_145_IOMUX_I2C0_SCL 0 -#define GPIO_145_IOMUX_GPIOxx 1 -#define GPIO_146_IOMUX_I2C0_SDA 0 -#define GPIO_146_IOMUX_GPIOxx 1 -#define GPIO_147_IOMUX_I2C1_SCL 0 -#define GPIO_147_IOMUX_GPIOxx 1 -#define GPIO_148_IOMUX_I2C1_SDA 0 -#define GPIO_148_IOMUX_GPIOxx 1 #define GPIO_2_EVENT GEVENT_8 -- To view, visit https://review.coreboot.org/c/coreboot/+/33761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59f958151f27ed4ca0eb1a87ade6102eec1e5061 Gerrit-Change-Number: 33761 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: soc/amd/picasso: Add code to support Romstage in RAM
by Martin Roth (Code Review) 09 Aug '19

09 Aug '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32415 Change subject: soc/amd/picasso: Add code to support Romstage in RAM ...................................................................... soc/amd/picasso: Add code to support Romstage in RAM AMD's Picasso SOC brings up memory before releasing the X86 processor, and jumps directly to Romstage. This adds the platform support for that. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I5ac62f6f3edb0c903fdc880fa655727ad2bc86bb --- M src/soc/amd/picasso/Kconfig A src/soc/amd/picasso/include/soc/romstage.ld A src/soc/amd/picasso/reset_vector.S 3 files changed, 187 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32415/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 129dedf..3d30b46b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -26,6 +26,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ROMSTAGE_IN_RAM select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/amd/picasso/include/soc/romstage.ld b/src/soc/amd/picasso/include/soc/romstage.ld new file mode 100644 index 0000000..4be3340 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/romstage.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM) +SECTIONS { + _JMP_IN_RAM = CONFIG_ROMSTAGE_ADDR + CONFIG_ROMSTAGE_MAX_SIZE - 0x1000; + . = _JMP_IN_RAM; + .resetram . : { *(.resetram) } + _RST_IN_RAM = CONFIG_ROMSTAGE_ADDR + CONFIG_ROMSTAGE_MAX_SIZE - 0x10; + . = _RST_IN_RAM; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} +#endif diff --git a/src/soc/amd/picasso/reset_vector.S b/src/soc/amd/picasso/reset_vector.S new file mode 100644 index 0000000..6a3bbfa --- /dev/null +++ b/src/soc/amd/picasso/reset_vector.S @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000, Ron Minnich rminnich(a)lanl.gov + * Advanced Computing Lab, LANL + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <arch/rom_segs.h> + +/* The resetram section keeps this code within reach of the first jmp to + * _start16bit. This functionality is contained within bootblock on most + * other systems, however this file is part of romstage which isn't subject + * to the same size limitations. + */ +.section ".resetram", "ax", %progbits + +.align 4096 +.code16 +.globl _start16bit +.type _start16bit, @function + +_start16bit: + cli + /* Save the BIST result */ + movl %eax, %ebp + + post_code(POST_RESET_VECTOR_CORRECT) + + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. Thanks to kmliu(a)sis.com.tw for this TLB fix. + */ + + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB*/ + + /* + * Load an IDT with NULL limit to prevent the 16bit IDT being used + * in protected mode before c_start.S sets up a 32bit IDT when entering + * RAM stage. In practise: CPU will shutdown on any exception. + * See IA32 manual Vol 3A 19.26 Interrupts. + */ + movl $nullidt_amd, %ebx + lidt %cs:(%bx) + + movl $fseg_gdt, %ebx + lgdtl %cs:(%bx) + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + /* Until now, the processor was executing in DRAM however the CS + * register's base and limit looked more like what you see after a + * traditional x86 reset. The value in CS has been 0xf000. Now that + * the GDT is loaded with flat descriptors, try to jump to + * 0x8:$__protected_start at its physical address in DRAM. + */ + ljmpl $ROM_CODE_SEG, $__protected_start + +.align 4 +.globl nullidt_amd +nullidt_amd: + .word 0 /* limit */ + .long 0 + .word 0 + + .align 4 + +gdt: +fseg_gdt: + .word gdt_end - gdt -1 + .long gdt + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes + for limit */ + + /* selgdt 0x10,flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + + /* selgdt 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +gdt_end: + +.code32 +.align 4 + +__protected_start: + post_code(POST_ENTER_PROTECTED_MODE) + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + +#if CONFIG(SSE) +enable_sse: + mov %cr4, %eax + or $CR4_OSFXSR, %ax + mov %eax, %cr4 +#endif /* CONFIG(SSE) */ + + cld + xor %eax, %eax + movl $(_car_region_end), %ecx + movl $(_car_region_start), %edi + sub %edi, %ecx + rep stosl + + mov $_car_stack_end, %esp + + /* Store BIST and an early timestamp at the top of the stack. See + * structure in soc/romstage.h for layout. + */ + rdtsc /* timestamp */ + push %edx + push %eax + push %ebp /* BIST */ + + and $0xfffffff0, %esp + sub $8, %esp + + jmp _romstage_in_ram_continue + +.section ".reset", "ax", %progbits +.code16 +.globl _start +_start: + .byte 0xe9 + .int _start16bit - ( . + 2 ) + /* Note: The above jump is hand coded to work around bugs in binutils. + * 5 byte are used for a 3 byte instruction. This works because x86 + * is little endian and allows us to use supported 32bit relocations + * instead of the weird 16 bit relocations that binutils does not + * handle consistently between versions because they are used so rarely. + */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac62f6f3edb0c903fdc880fa655727ad2bc86bb Gerrit-Change-Number: 32415 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: mediatek/mt8183: Add display driver
by yongqiang niu (Code Review) 09 Aug '19

09 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31478 Change subject: mediatek/mt8183: Add display driver ...................................................................... mediatek/mt8183: Add display driver BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/ddp.h 5 files changed, 602 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31478/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..a089236 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,36 @@ setup_usb_host(); } +static void display_startup(void) +{ + int ret = 0; + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "start display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..225a969 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ddp.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c new file mode 100644 index 0000000..2e2c0d2 --- /dev/null +++ b/src/soc/mediatek/mt8183/ddp.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); + + write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0); + + write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L); + + write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR); + + write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0); + + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +static void ovl_layer_enable(u32 idx) +{ + write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void rdma_start(u32 idx) +{ + setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); +} + +static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh) +{ + u32 threshold; + u32 reg; + u32 fifo_size; + + /* Config width */ + clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); + + /* Config height */ + clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + + fifo_size = RDMA_FIFO_SIZE_0 * KiB; + + threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[idx]->fifo_con, reg); +} + +static void color_start(u32 width, u32 height) +{ + write32(&disp_color->width, width); + write32(&disp_color->height, height); + write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color->start, BIT(0)); +} + +static void aal_start(u32 width, u32 height) +{ + write32(&disp_aal->size, height << 16 | width); + write32(&disp_aal->en, PQ_EN); +} + +static void ccorr_start(u32 width, u32 height) +{ + write32(&disp_ccorr->size, height << 16 | width); + write32(&disp_ccorr->cfg, PQ_RELAY_MODE); + write32(&disp_ccorr->en, PQ_EN); +} + +static void dither_start(u32 width, u32 height) +{ + write32(&disp_dither->size, height << 16 | width); + write32(&disp_dither->cfg, PQ_RELAY_MODE); + write32(&disp_dither->en, PQ_EN); +} + +static void gamma_start(u32 width, u32 height) +{ + write32(&disp_gamma->size, height << 16 | width); + write32(&disp_gamma->en, PQ_EN); +} + +static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[idx]->layer[0].con, fmt << 12); + write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(idx); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + + /* Setup OVL */ + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + u32 color = 0; + + if (idx == 0) + color = 0xFF0000FF; + + ovl_set_roi(idx, width, height, color); + } + + /* Setup RDMA0 */ + idx = 0; + rdma_config(idx, width, height, vrefresh); + + /* Setup Color */ + color_start(width, height); + + /* Setup CCORR */ + ccorr_start(width, height); + + /* Setup AAL */ + aal_start(width, height); + + /* Setup GAMMA */ + gamma_start(width, height); + + /* Setup DITHER */ + dither_start(width, height); + + /* Setup main path connection */ + disp_config_main_path_connection(); + + /* Setup main path mutex */ + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); +} + +static void disp_m4u_port_off(void) +{ + write32((void *)(SMI_LARB0 + 0x380), 0); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + disp_m4u_port_off(); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 idx = 0; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + main_disp_path_setup(width, height, vrefresh); + + rdma_start(idx); + + ovl_layer_config(idx, fmt, bpp, width, height); + + ovl_bgclr_in_sel(idx+1); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..88653eb 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -53,6 +53,19 @@ IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h new file mode 100644 index 0000000..38f66e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -0,0 +1,326 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include <soc/addressmap.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[889]; /* 0x11C */ + u32 disp_ovl0_mout_en; /* 0xF00 */ + u32 disp_ovl0_2l_mout_en; /* 0xF04 */ + u32 disp_ovl1_2l_mout_en; /* 0xF08 */ + u32 disp_dither0_mout_en; /* 0xF0C */ + u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */ + u32 disp_path0_sel_in; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 dsi0_sel_in; /* 0xF2C */ + u32 dpi0_sel_in; /* 0xF30 */ + u32 reserved_0xF34; /* 0xF34 */ + u32 disp_ovl0_2l_sel_in; /* 0xF38 */ + u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */ + u32 disp_rdma0_sout_sel_in; /* 0xF50 */ + u32 disp_rdma1_sout_sel_in; /* 0xF54 */ + u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */ + u32 dpi0_sel_sout_sel_in; /* 0xF64 */ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, reserved_0x11C, 0x11C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF00); +check_member(mmsys_cfg_regs, reserved_0xF10, 0xF10); +check_member(mmsys_cfg_regs, disp_path0_sel_in, 0xF24); +check_member(mmsys_cfg_regs, disp_ovl0_2l_sel_in, 0xF38); +check_member(mmsys_cfg_regs, reserved_0xF3C, 0xF3C); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel_in, 0xF50); +check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_GALS_COMMON0 = BIT(3), + CG_CON0_GALS_COMMON1 = BIT(4), + CG_CON0_DISP_OVL0 = BIT(20), + CG_CON0_DISP_OVL0_2L = BIT(21), + CG_CON0_DISP_OVL1_2L = BIT(22), + CG_CON0_DISP_RDMA0 = BIT(23), + CG_CON0_DISP_RDMA1 = BIT(24), + CG_CON0_DISP_WDMA0 = BIT(25), + CG_CON0_DISP_COLOR0 = BIT(26), + CG_CON0_DISP_CCORR0 = BIT(27), + CG_CON0_DISP_AAL0 = BIT(28), + CG_CON0_DISP_GAMMA0 = BIT(29), + CG_CON0_DISP_DITHER0 = BIT(30), + CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_GALS_COMMON0 | + CG_CON0_GALS_COMMON1 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_DSI0 = BIT(0), + CG_CON1_DISP_DSI0_INTERFACE = BIT(1), + CG_CON1_DISP_26M = BIT(7), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_RDMA0 = BIT(0), + OVL0_MOUT_EN_OVL0_2L = BIT(4), + OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0), + OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4), + DITHER0_MOUT_EN_DISP_DSI0 = BIT(0), +}; + +enum { + DISP_PATH0_SEL_IN_OVL0 = 0, + DISP_PATH0_SEL_IN_OVL0_2L = 1, + DSI0_SEL_IN_DITHER0_MOUT = 0, + DSI0_SEL_IN_RDMA0 = 1, + RDMA0_SOUT_SEL_IN_DSI0 = 0, + RDMA0_SOUT_SEL_IN_COLOR = 1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_RDMA0 = BIT(0), + MUTEX_MOD_DISP_RDMA1 = BIT(1), + MUTEX_MOD_DISP_OVL0 = BIT(9), + MUTEX_MOD_DISP_OVL0_2L = BIT(10), + MUTEX_MOD_DISP_OVL1_2L = BIT(11), + MUTEX_MOD_DISP_WDMA0 = BIT(12), + MUTEX_MOD_DISP_COLOR0 = BIT(13), + MUTEX_MOD_DISP_CCORR0 = BIT(14), + MUTEX_MOD_DISP_AAL0 = BIT(15), + MUTEX_MOD_DISP_GAMMA0 = BIT(16), + MUTEX_MOD_DISP_DITHER0 = BIT(17), + MUTEX_MOD_DISP_PWM0 = BIT(28), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0| MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u32 reserved_0x018[2]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u32 reserved_0x0B0[4]; + struct { + u32 ctrl; + u32 reserved0; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u32 reserved1[3]; + } rdma[4]; + u32 reserved_0x140[880]; + u32 reserved_0xF00[16]; + u32 l0_addr; + u32 reserved_0xF44[7]; + u32 l1_addr; + u32 reserved_0xF64[7]; + u32 l2_addr; + u32 reserved_0xF84[7]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, reserved_0x018, 0x018); +check_member(disp_ovl_regs, roi_size, 0x020); +check_member(disp_ovl_regs, reserved_0x0B0, 0x0B0); +check_member(disp_ovl_regs, reserved_0x140, 0x140); +check_member(disp_ovl_regs, reserved_0xF00, 0xF00); +check_member(disp_ovl_regs, l0_addr, 0xF40); +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u32 reserved0[2]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u32 reserved1; + u32 mem_con; + u32 reserved2; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_gmc_setting_1; + u32 mem_slow_con; + u32 mem_gmc_setting_2; + u32 fifo_con; + u32 reserved3[4]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_FIFO_SIZE_0 = 5, /* 5K */ + RDMA_VREFRESH = 60, /* vrefresh 60HZ */ + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma[2] = { + (void *)DISP_RDMA0_BASE, + (void *)DISP_RDMA1_BASE, +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +struct disp_pq_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), +}; + +static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Gerrit-Change-Number: 31478 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

9 61

Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 de...
by Sumeet R Pawnikar (Code Review) 09 Aug '19

09 Aug '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33131 Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 degree C ...................................................................... mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 degree C PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFA. Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33131/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..595fcf5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -163,6 +163,9 @@ register "tcc_offset" = "10" + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Gerrit-Change-Number: 33131 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 75 de...
by Sumeet R Pawnikar (Code Review) 09 Aug '19

09 Aug '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33130 Change subject: mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 75 degree C ...................................................................... mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 75 degree C PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFA. Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33130/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 767df1f..b6aa041 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -164,6 +164,9 @@ register "tcc_offset" = "1" + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Gerrit-Change-Number: 33130 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 12

Change in ...coreboot[master]: WIP: riscv: Implement FIT for RISC-V
by Philipp Hug (Code Review) 08 Aug '19

08 Aug '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31215 Change subject: WIP: riscv: Implement FIT for RISC-V ...................................................................... WIP: riscv: Implement FIT for RISC-V Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 --- M payloads/Kconfig M src/arch/riscv/Makefile.inc A src/arch/riscv/fit_payload.c M src/soc/sifive/fu540/Kconfig 4 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31215/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index c7a7ba6..0c5ce8f 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 + depends on ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..12609d4 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -139,6 +139,7 @@ ramstage-y += tables.c ramstage-y += payload.S ramstage-$(ARCH_RISCV_PMP) += pmp.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c new file mode 100644 index 0000000..2176095 --- /dev/null +++ b/src/arch/riscv/fit_payload.c @@ -0,0 +1,166 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootmem.h> +#include <stdlib.h> +#include <program_loading.h> +#include <string.h> +#include <commonlib/compression.h> +#include <commonlib/cbfs_serialized.h> +#include <lib.h> +#include <fit.h> +#include <endian.h> + +#define MAX_KERNEL_SIZE (64*MiB) + +static bool fit_place_kernel(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /** + * The Image must be placed text_offset bytes from a 2MB aligned base + * address anywhere in usable system RAM and called there. The region + * between the 2 MB aligned base address and the start of the image has + * no special significance to the kernel, and may be used for other + * purposes. + * + * If the reserved memory (BL31 for example) is smaller than text_offset + * we can use the 2 MiB base address, otherwise use the next 2 MiB page. + * It's not mandatory, but wastes less memory below the kernel. + */ + start = ALIGN_DOWN(range_entry_base(r), 2 * MiB); + + if (start < range_entry_base(r)) + start += 2 * MiB; + /** + * At least image_size bytes from the start of the image must be free + * for use by the kernel. + */ + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + * The region->offset is usually 0 on kernel >v4.6 and kernel_base + kernel_size + * on kernel <v4.6. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + bool place_anywhere; + void *arg = NULL; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot an RISCV kernel!\n"); + return false; + } + + /* Update kernel size from image header, if possible */ + kernel->size = 0x2000000; //get_kernel_size(config->kernel_node); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + + if (!bootmem_walk(fit_place_kernel, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * NOTE: versions prior to v4.6 cannot make use of memory below the + * physical offset of the Image so it is recommended that the Image be + * placed as close as possible to the start of system RAM. + * + * For kernel <v4.6 the INITRD and FDT can't be placed below the kernel. + * In that case set region offset to an address on top of kernel. + */ + + place_anywhere = false; + printk(BIOS_DEBUG, "FIT: Placing FDT and INITRD %s\n", + place_anywhere ? "anywhere" : "on top of kernel"); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = 0; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + if (place_anywhere) + fdt->offset = 0; + else + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..20645da 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,7 @@ int default 0 +config HEAP_SIZE + default 0x10000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 Gerrit-Change-Number: 31215 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Update vboot submodule to upstream master
by Joel Kitching (Code Review) 08 Aug '19

08 Aug '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33858 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id dac763c7: 2019-05-10 10:43:55 -0700 - (Make vboot -Wtype-limits compliant) to commit id 1851825b: 2019-06-26 14:24:47 +0000 - (vboot: remove VerifyMemberInside function) This brings in 51 new commits. Change-Id: Ia96347d8ed94db6f0ec5f5108cb98ab0c4087bd4 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33858/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index dac763c..1851825 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit dac763c782ce05476dec02e855f349d2b6f3a910 +Subproject commit 1851825b05d266509c4157d1413c0d853a9add28 -- To view, visit https://review.coreboot.org/c/coreboot/+/33858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia96347d8ed94db6f0ec5f5108cb98ab0c4087bd4 Gerrit-Change-Number: 33858 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mainboard/emulation/qemu-aarch64: Add new board for ARMv8
by Asami Doi (Code Review) 08 Aug '19

08 Aug '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33387 Change subject: mainboard/emulation/qemu-aarch64: Add new board for ARMv8 ...................................................................... mainboard/emulation/qemu-aarch64: Add new board for ARMv8 This CL adds new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt -cpu cortex-a53 \ -bios build/coreboot.rom -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <doiasami1219(a)gmail.com> --- M src/cpu/armltd/Kconfig M src/cpu/armltd/Makefile.inc A src/cpu/armltd/cortex-a53/Kconfig A src/mainboard/emulation/qemu-aarch64/Kconfig A src/mainboard/emulation/qemu-aarch64/Kconfig.name A src/mainboard/emulation/qemu-aarch64/Makefile.inc A src/mainboard/emulation/qemu-aarch64/board_info.txt A src/mainboard/emulation/qemu-aarch64/cbmem.c A src/mainboard/emulation/qemu-aarch64/devicetree.cb A src/mainboard/emulation/qemu-aarch64/mainboard.c A src/mainboard/emulation/qemu-aarch64/mainboard.h A src/mainboard/emulation/qemu-aarch64/media.c A src/mainboard/emulation/qemu-aarch64/memlayout.ld A src/mainboard/emulation/qemu-aarch64/mmio.c A src/mainboard/emulation/qemu-aarch64/timer.c 15 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33387/1 diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig index af0c5c5..fc01735 100644 --- a/src/cpu/armltd/Kconfig +++ b/src/cpu/armltd/Kconfig @@ -1 +1,2 @@ source src/cpu/armltd/cortex-a9/Kconfig +source src/cpu/armltd/cortex-a53/Kconfig diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc index 014742f..cd6acf1 100644 --- a/src/cpu/armltd/Makefile.inc +++ b/src/cpu/armltd/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9 +subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A53) += cortex-a53 diff --git a/src/cpu/armltd/cortex-a53/Kconfig b/src/cpu/armltd/cortex-a53/Kconfig new file mode 100644 index 0000000..1cbfc33 --- /dev/null +++ b/src/cpu/armltd/cortex-a53/Kconfig @@ -0,0 +1,10 @@ +config CPU_ARMLTD_CORTEX_A53 + bool + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + default n + +if CPU_ARMLTD_CORTEX_A53 + +endif diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig new file mode 100644 index 0000000..9fda646 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# Emulation for QEMU 2.8 ARM Virtual Machine (alias of virt-2.8) +# https://wiki.qemu.org/Documentation/Platforms/ARM + +# To execute, do: +# export QEMU_AUDIO_DRV = none +# qemu-system-aarch64 -M virt -m 1024M -cpu cortex-a53 -nographic -bios build/coreboot.rom + +if BOARD_EMULATION_QEMU_AARCH64 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_ARMLTD_CORTEX_A53 + select DRIVERS_UART_PL011 + select CONSOLE_SERIAL + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select BOARD_ROMSIZE_KB_4096 + select BOOT_DEVICE_NOT_SPI_FLASH + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + string + default emulation/qemu-aarch64 + +config MAINBOARD_PART_NUMBER + string + default "QEMU AArch64" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "ARM Ltd." + +endif # BOARD_EMULATION_QEMU_AARCH64 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig.name b/src/mainboard/emulation/qemu-aarch64/Kconfig.name new file mode 100644 index 0000000..9789823 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_AARCH64 + bool "QEMU AArch64 (virt)" diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc new file mode 100644 index 0000000..e120bec --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-aarch64/board_info.txt b/src/mainboard/emulation/qemu-aarch64/board_info.txt new file mode 100644 index 0000000..e3ecc19 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU AArch64 (virt) +Category: emulation +Board URL: https://wiki.qemu.org/Documentation/Platforms/ARM diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c new file mode 100644 index 0000000..635fe4b --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <cbmem.h> +#include <symbols.h> +#include <device/mmio.h> +#include "mainboard.h" + +#define PATTERN1 0x55 +#define PATTERN2 0xaa + +/* Returns 1 if mebibyte mb is present and 0 otherwise. */ +static int probe_mb(int mb) +{ + char *ptr = (char *)0x60000000 + (mb << 20) + 0xfffff; + char old; + if (ptr < (char *)&_eprogram) { + /* Don't probe below _end to avoid accidentally clobering + oneself. */ + return 1; + } + + old = read8(ptr); + write8(ptr, PATTERN1); + if (read8(ptr) != PATTERN1) + return 0; + write8(ptr, PATTERN2); + if (read8(ptr) != PATTERN2) + return 0; + write8(ptr, old); + return 1; +} + +int probe_ramsize(void) +{ + int i; + int discovered = 0; + static int saved_result; + if (saved_result) + return saved_result; + /* Compact binary search. */ + /* 1 GiB is the largest supported RAM by this machine. */ + for (i = 9; i >= 0; i--) + if (probe_mb(discovered | (1 << i))) + discovered |= (1 << i); + discovered++; + saved_result = discovered; + return discovered; +} + +void *cbmem_top(void) +{ + return _dram + (probe_ramsize() << 20); +} diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb new file mode 100644 index 0000000..258d7ba --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip cpu/armltd/cortex-a53 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c new file mode 100644 index 0000000..f0b90f1 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or, at your option, any later + * version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <halt.h> +#include "mainboard.h" +#include <edid.h> +#include <device/mmio.h> + +static void init_gfx(void) +{ + uint32_t *pl111; + struct edid edid; + /* width is at most 4096 */ + /* height is at most 1024 */ + int width = 800, height = 600; + uint32_t framebuffer = 0x4c000000; + pl111 = (uint32_t *)0x10020000; + write32(pl111, (width / 4) - 4); + write32(pl111 + 1, height - 1); + /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if + we ever go for real hw. */ + /* framebuffer address offset. Has to be in vram. */ + write32(pl111 + 4, framebuffer); + write32(pl111 + 7, 0); + write32(pl111 + 10, 0xff); + write32(pl111 + 6, (5 << 1) | 0x801); + + edid.framebuffer_bits_per_pixel = 32; + edid.bytes_per_line = width * 4; + edid.x_resolution = width; + edid.y_resolution = height; + + set_vbe_mode_info_valid(&edid, framebuffer); +} + +static void mainboard_enable(struct device *dev) +{ + int discovered; + if (!dev) { + printk(BIOS_EMERG, "No dev0; die\n"); + halt(); + } + + discovered = probe_ramsize(); + printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered); + ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10); + cbmem_recovery(0); + init_gfx(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.h b/src/mainboard/emulation/qemu-aarch64/mainboard.h new file mode 100644 index 0000000..b6927ea --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or, at your option, any later + * version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef QEMU_AARCH64_MAINBOARD_H +#define QEMU_AARCH64_MAINBOARD_H + +/* Returns RAM size in mebibytes. */ +int probe_ramsize(void); + +#endif diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c new file mode 100644 index 0000000..c9c3a34 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld new file mode 100644 index 0000000..03db138 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Asami Doi <d0iasm.pub(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Memory map for QEMU virt machine since + * a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019): + * + * 0x0000_0000: Flash memory + * 0x0800_0000: I/O map address + * 0x6000_0000: RAM + */ + +#define VIRT_FLASH_START 0x00000000 +#define VIRT_IO_START 0x08000000 +#define VIRT_DRAM_START 0x60000000 + +/* + * This map is designed to work with new qemu virt memory layout and + * with -bios option which neatly puts coreboot into flash and so payloads + * can find CBFS and we don't risk overwriting CBFS. + * + * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash + * and -bios was unusable as $pc pointed to 0 which was zero-filled as a + * workaround we suggested using -kernel but this still had all the issues + * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends + * up exactly at addresses needed to load Linux. + */ +SECTIONS +{ + BOOTBLOCK(VIRT_FLASH_START, 64K) + + DRAM_START(VIRT_DRAM_START) + STACK(VIRT_DRAM_START, 64K) + ROMSTAGE(VIRT_DRAM_START + 0x10000, 128K) + RAMSTAGE(VIRT_DRAM_START + 0x30000, 16M) + + /* TODO: Implement MMU support and move TTB to a better location. */ + TTB(0x61030000, 16K) +} diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c new file mode 100644 index 0000000..1b9a669 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> + +#define VIRT_UART_IO_ADDRESS (0x09000000) + +uintptr_t uart_platform_base(int idx) +{ + return VIRT_UART_IO_ADDRESS; +} diff --git a/src/mainboard/emulation/qemu-aarch64/timer.c b/src/mainboard/emulation/qemu-aarch64/timer.c new file mode 100644 index 0000000..599a872 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/timer.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void udelay(unsigned int n); +void udelay(unsigned int n) +{ + /* TODO provide delay here. */ +} + +int init_timer(void); +int init_timer(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Gerrit-Change-Number: 33387 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

5 74

Change in ...coreboot[master]: src/superio/aspeed/common: Add ACPI Template for Autogen Feature
by Christian Walter (Code Review) 07 Aug '19

07 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33250 Change subject: src/superio/aspeed/common: Add ACPI Template for Autogen Feature ...................................................................... src/superio/aspeed/common: Add ACPI Template for Autogen Feature Add ACPI Template for Autogen Feature. Change-Id: Ic356af269e381bd5310d9be057bc16f9d5186934 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- A src/superio/aspeed/common/acpi/superio.asl 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33250/1 diff --git a/src/superio/aspeed/common/acpi/superio.asl b/src/superio/aspeed/common/acpi/superio.asl new file mode 100644 index 0000000..6b8b8f6 --- /dev/null +++ b/src/superio/aspeed/common/acpi/superio.asl @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +Device (SIO0) +{ + Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/33250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic356af269e381bd5310d9be057bc16f9d5186934 Gerrit-Change-Number: 33250 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

6 14

Change in ...coreboot[master]: kukui/mainboard: Add mt8183 display usecase
by yongqiang niu (Code Review) 07 Aug '19

07 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31517 Change subject: kukui/mainboard: Add mt8183 display usecase ...................................................................... kukui/mainboard: Add mt8183 display usecase BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31517/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..950dca4 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,31 @@ setup_usb_host(); } +static void display_startup(void) +{ + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "Starting display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Gerrit-Change-Number: 31517 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019