coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/google/octopus: Disable WLAN prior the entry of S5
by Kane Chen (Code Review) 15 Aug '19

15 Aug '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32246 Change subject: mb/google/octopus: Disable WLAN prior the entry of S5 ...................................................................... mb/google/octopus: Disable WLAN prior the entry of S5 ODM reported issues that some systems can't be shutdown to S5 very occasionally. ODM found issue is gone if they remove the WLAN card. So, this change to disable WLAN before system enters S5. This change is validated by ODM and it does help issue. BUG=b:129377927 Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32246/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 5326118..3305c02 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -341,6 +341,8 @@ static const struct pad_config sleep_s5_gpio_table[] = { /* BT_DISABLE_L */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME), + /* WLAN_DISABLE_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 0, DEEP, NONE, Tx0RxDCRx1, SAME), }; const struct pad_config *__weak -- To view, visit https://review.coreboot.org/c/coreboot/+/32246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595 Gerrit-Change-Number: 32246 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: mediatek/mt8183: Select VBOOT_MIGRATE_WORKING_DATA
by Tristan Hsieh (Code Review) 14 Aug '19

14 Aug '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33558 Change subject: mediatek/mt8183: Select VBOOT_MIGRATE_WORKING_DATA ...................................................................... mediatek/mt8183: Select VBOOT_MIGRATE_WORKING_DATA The vboot working data is inaccessible to normal world payloads. Migrate it into CBMEM. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I786da91ae117d4d9a4fe38d9c0cf410e2de30030 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33558/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index f96282c..bdfd2e5 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -14,6 +14,7 @@ if SOC_MEDIATEK_MT8183 config VBOOT + select VBOOT_MIGRATE_WORKING_DATA select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/33558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786da91ae117d4d9a4fe38d9c0cf410e2de30030 Gerrit-Change-Number: 33558 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/packardbell/ms2290/Kconfig: Remove ARCH_x options
by Arthur Heymans (Code Review) 12 Aug '19

12 Aug '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33507 Change subject: mb/packardbell/ms2290/Kconfig: Remove ARCH_x options ...................................................................... mb/packardbell/ms2290/Kconfig: Remove ARCH_x options Those are already selected in cpu/intel/model_2065x/Kconfig. Change-Id: I7421faa24b8a95d2780bce0651cde0bfeb357833 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/packardbell/ms2290/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33507/1 diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index c6a1e12..6315591 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -3,9 +3,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ARCH_BOOTBLOCK_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select NORTHBRIDGE_INTEL_NEHALEM select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/33507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7421faa24b8a95d2780bce0651cde0bfeb357833 Gerrit-Change-Number: 33507 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: soc/sifive/fu540: add code for spi and map flash to memory spaces
by Xiang Wang (Code Review) 12 Aug '19

12 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33055 Change subject: soc/sifive/fu540: add code for spi and map flash to memory spaces ...................................................................... soc/sifive/fu540: add code for spi and map flash to memory spaces SiFive's ZSBL has initialized flash, but only 16MB of space is available. 1. add code for spi 2. add code to map flash to memory spaces 3. to support HiFive Unleashed's ISSI Flash (IS25WP256D) Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.inc A src/drivers/spi/issi.c M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/spi.c A src/soc/sifive/fu540/spi_internal.h 10 files changed, 946 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33055/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502..da46071 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -130,6 +130,13 @@ Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST. +config SPI_FLASH_ISSI + bool + default y if SPI_FLASH_INCLUDE_ALL_DRIVERS + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by ISSI. + config SPI_FLASH_STMICRO bool default y if SPI_FLASH_INCLUDE_ALL_DRIVERS diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index e55233e..b532398 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -25,6 +25,7 @@ $(1)-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c $(1)-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c $(1)-$(CONFIG_SPI_FLASH_SST) += sst.c +$(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c $(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c $(1)-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c new file mode 100644 index 0000000..305f0ae --- /dev/null +++ b/src/drivers/spi/issi.c @@ -0,0 +1,367 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <stdlib.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <string.h> + +#include "spi_flash_internal.h" + +/* software reset enable */ +#define CMD_ISSI_RST 0x66 +/* software reset */ +#define CMD_ISSI_RST 0x99 +/* read status register */ +#define CMD_ISSI_RDSR 0x05 +/* write status register */ +#define CMD_ISSI_WRSR 0x01 +/* write enable */ +#define CMD_ISSI_WREN 0x06 +/* write disable */ +#define CMD_ISSI_WRDI 0x04 +/* read bank register */ +#define CMD_ISSI_RDBR 0x16 +/* write bank register */ +#define CMD_ISSI_WRBRV 0x17 +/* normal read */ +#define CMD_ISSI_NORD 0x03 +/* normal read with 4Bytes address*/ +#define CMD_ISSI_4NORD 0x13 +/* page program, up to 256bytes */ +#define CMD_ISSI_PP 0x02 +/* page program with 4Bytes address, up to 256bytes */ +#define CMD_ISSI_4PP 0x12 +/* sector erase, section size is 4kbytes */ +#define CMD_ISSI_SEC 0x20 +/* sector erase with 4Bytes address, section size is 4KBytes */ +#define CMD_ISSI_4SEC 0x21 + +struct issi_spi_flash_params { + u16 model; + u32 size; + u32 sector_size; + u8 status_cmd; + const char *name; + const struct spi_flash_ops *ops; +}; + +static const struct spi_flash_ops spi_flash_ops = { + .read = issi_flash_cmd_read, + .write = issi_flash_cmd_write, + .erase = issi_flash_cmd_erase, + .status = spi_flash_cmd_status, +}; + + +static struct issi_spi_flash_params issi_spi_flash_table[] = { + { + .model = 0x6019 + .size = 32 * 1024 * 1024, + .sector_size = 4 * 1024, + .status_cmd = CMD_ISSI_RDSR, + .name = "IS25LP256D", + .ops = spi_flash_ops + }, + { + .model = 0x7019, + .size = 32 * 1024 * 1024, + .sector_size = 4 * 1024, + .status_cmd = CMD_ISSI_RDSR, + .name = "IS25WP256D", + .ops = spi_flash_ops + } +}; + +static int issi_do_cmd(const struct spi_flash *flash, + void *cmd, size_t cmd_len) +{ + int ret = 0; + struct spi_op vectors[] = { + [0] = { .dout = cmd, .bytesout = cmd_len, + .din = NULL, .bytesin = 0, } + }; + do { + ret = spi_claim_bus(&flash->spi); + if (ret) + break; + ret = spi_xfer_vector(&flash->spi, vectors, 1); + if (ret) + break; + spi_release_bus(&flash->spi); + } while (0); + return ret; +} + +static int issi_do_read_cmd(const struct spi_flash *flash, + void *cmd, size_t cmd_len, + void *data, size_t data_len) +{ + int ret = 0; + struct spi_op vectors[] = { + [0] = { .dout = cmd, .bytesout = cmd_len, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = data, .bytesin = data_len }, + }; + size_t count = (data_len == 0 ? 1 : 2); + do { + ret = spi_claim_bus(&flash->spi); + if (ret) + break; + ret = spi_xfer_vector(&flash->spi, vectors, count); + if (ret) + break; + spi_release_bus(&flash->spi); + } while (0); + return ret; +} + +static int issi_do_write_cmd(const struct spi_flash *flash, + void *cmd, size_t cmd_len, + void *data, size_t data_len) +{ + int ret = 0; + struct spi_op vectors[] = { + [0] = { .dout = cmd, .bytesout = cmd_len, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = data, .bytesout = data_len, + .din = NULL, .bytesin = 0 }, + }; + size_t count = (data_len == 0 ? 1 : 2); + do { + ret = spi_claim_bus(&flash->spi); + if (ret) + break; + ret = spi_xfer_vector(&flash->spi, vectors, count); + if (ret) + break; + spi_release_bus(&flash->spi); + } while (0); + return ret; +} + +static int issi_software_reset(const struct spi_flash *flash) +{ + int ret = 0; + static const u8 cmd_reset_enable = CMD_ISSI_RSTEN; + static const u8 cmd_reset = CMD_ISSI_RST; + do { + ret = issi_do_cmd(flash, &cmd_reset_enable, 1); + if (ret) + break; + ret = issi_do_cmd(flash, &cmd_reset, 1); + if (ret) + break; + } while (0); + if (ret) + printk(BIOS_WARNING, "SF: Resetting failed\n"); + return ret; +} + +static int issi_enable_writing(const struct spi_flash *flash) +{ + static const u8 cmd = CMD_ISSI_WREN; + int ret = issi_do_cmd(flash, &cmd, 1); + if (ret) + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + return ret; +} + +static int issi_disable_writing(const struct spi_flash *flash) +{ + static const u8 cmd = CMD_ISSI_WRDI; + int ret = issi_do_cmd(flash, &cmd, 1); + if (ret) + printk(BIOS_WARNING, "SF: Disabling Write failed\n"); + return ret; +} + +static int issi_flash_cmd_read(const struct spi_flash *flash, + u32 offset, size_t len, void *data) +{ + int ret = 0; + if (flash->size <= 32 * 1024 * 1024) { + u8 cmd[] = { + CMD_ISSI_NORD, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff, + }; + ret = issi_do_read_cmd(flash, cmd, sizeof(cmd), data, len); + } else { + u8 cmd[] = { + CMD_ISSI_4NORD, + (offset >> 24) & 0xff, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff, + } + ret = issi_do_read_cmd(flash, cmd, sizeof(cmd), data, len); + } + if (ret) + printk(BIOS_WARNING, "SF: Failed to send read command " + "(%zu bytes): %d\n", len, ret); + return ret; +} + +static int issi_flash_cmd_write(const struct spi_flash *flash, + u32 offset, size_t len, void *data) +{ + int ret = 0; + + ret = issi_enable_writing(flash); + if (ret) + return ret; + + do { + u8 bank = offset >> 24; + u8 cmd[4] = { + CMD_ISSI_PP, + (offset >> 2) & 0xff, + (offset >> 1) & 0xff, + (offset >> 0) & 0xff, + }; + + size_t wlen = (len > 256 ? 256 : len); + + if (flash->size <= 32 * 1024 * 1024) { + u8 cmd[4] = { + CMD_ISSI_PP, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff + }; + ret = issi_do_write_cmd(flash, cmd, sizeof(cmd), + data, wlen); + } else { + u8 cmd[5] = { + CMD_ISSI_4PP, + (offset >> 24) & 0xff, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff + }; + ret = issi_do_write_cmd(flash, cmd, sizeof(cmd), + data, wlen); + } + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send write command" + " (%zu bytes): %d\n", wlen, ret); + return ret; + } + + len = len - wlen; + offset = offset + wlen; + data = (void *)((uintptr_t)data + wlen); + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + return ret; + } while (len); + + ret = issi_disable_writing(flash); + + return ret; +} + +static int issi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, + size_t len) +{ + int ret = 0; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_WARNING, "SF: Erase offset/length not multiple of" + " erase size\n"); + return -1; + } + if (len == 0) { + printk(BIOS_WARNING, "SF: Erase length cannot be 0\n"); + return -1; + } + + ret = issi_enable_writing(flash); + if (ret) + return ret; + + u32 end = offset + len; + + while (offset < end) { + if (flash->size <= 32 * 1024 * 1024) { + u8 cmd[4] = { + CMD_ISSI_PP, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff + }; + ret = issi_do_cmd(flash, cmd, sizeof(cmd)); + } else { + u8 cmd[5] = { + CMD_ISSI_4PP, + (offset >> 24) & 0xff, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff + }; + ret = issi_do_cmd(flash, cmd, sizeof(cmd)); + } + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send erase command" + " (offset: %#04x): %d\n", offset, ret); + return ret; + } + + offset = offset + erase_size; + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + return ret; + } + + ret = issi_disable_writing(flash); + + return ret; +} + +int spi_flash_probe_issi(const struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash) +{ + size_t i; + u16 model; + const struct issi_spi_flash_params *params; + + for (i = 0; i < ARRAY_SIZE(issi_spi_flash_table); ++i) { + params = &sst_spi_flash_table[i]; + model = (idcode[1] << 8) | idcode[2]; + if (params->model == model) + break; + } + + if (i == ARRAY_SIZE(issi_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported ISSI ID %04x\n", model); + return -1; + } + + memcpy(&flash->spi, spi, sizeof(*spi)); + flash->name = params->name; + flash->sector_size = params->sector_size; + flash->size = params->size; + flash->status_cmd = params->status_cmd; + + flash->ops = params->ops; + + issi_software_reset(flash); + + return 0; +} diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 263297e..35a64d3 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -12,12 +12,15 @@ # GNU General Public License for more details. bootblock-y += memlayout.ld +bootblock-y += media.c romstage-y += memlayout.ld romstage-y += romstage.c +romstage-y += media.c ramstage-y += memlayout.ld ramstage-y += fixup_fdt.c +ramstage-y += media.c DTB=build/hifive-unleashed.dtb diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..cd52bba --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <soc/spi.h> + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &mdev.rdev; +} + +const static struct fu540_spi_mmap_config spi_mmap_config = { + .cmd_en = 1, + .addr_len = 4, + .pad_cnt = 6, + .cmd_proto = FU540_SPI_PROTO_S, + .addr_proto = FU540_SPI_PROTO_Q, + .data_proto = FU540_SPI_PROTO_Q, + .cmd_code = 0xec, + .pad_code = 0 +}; + +void boot_device_init(void) +{ + const static uint8_t reset_en = 0x66; + const static uint8_t reset = 0x99; + struct spi_slave slave; + + /* initialize the spi controller */ + spi_setup_slave(0, 0, &slave); + + /* software reset flash chip */ + spi_xfer(&slave, &reset_en, 0, NULL, 0); + spi_xfer(&slave, &reset, 0, NULL, 0); + + /* map flash to memory space */ + fu540_spi_mmap(&slave, &spi_mmap_config); +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 4f62f3e..3c97c08 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,13 +15,13 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +bootblock-y += spi.c bootblock-y += bootblock.c bootblock-y += clock.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +romstage-y += spi.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c @@ -29,7 +29,7 @@ ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +ramstage-y += spi.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h new file mode 100644 index 0000000..543f9b2 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#include <spi-generic.h> + +/* Data Pins: MOSI MISO */ +#define FU540_SPI_PROTO_S 0 +/* Data Pins: DQ0 DQ1 */ +#define FU540_SPI_PROTO_D 1 +/* Data Pins: DQ0 DQ1 DQ2 DQ3 */ +#define FU540_SPI_PROTO_Q 2 + +/* send MSB first */ +#define FU540_SPI_ENDIAN_BIG 0 +/* send LSB first */ +#define FU540_SPI_ENDIAN_LITTLE 1 + +/* inactive state of SCK is logical 0 */ +#define FU540_SPI_PHA_LOW 0 +/* inactive state of SCK is logical 1 */ +#define FU540_SPI_PHA_HIGH 1 + +/* data is sampled on leading edge */ +#define FU540_SPI_POL_LEADING 0 +/* data is sampled on trailing edge */ +#define FU540_SPI_POL_TRAILING 1 + +struct fu540_spi_config { + /* speed of spi interface */ + unsigned int freq; + /* serial clock phase */ + unsigned int pha; + /* serial clock polarity */ + unsigned int pol; + unsigned int protocol; + unsigned int endianness; + /* up to 8bits */ + unsigned int bits_per_frame; +}; + +/* more detailed spi configuration */ +int fu540_spi_setup(unsigned int bus, unsigned int cs, struct spi_slave *slave, + struct fu540_spi_config *config); + +/* This structure is used to describe the read command of SPI FLASH. */ +struct fu540_spi_mmap_config { + /* enable sending of command */ + unsigned int cmd_en; + /* number of address bytes (0-4) */ + unsigned int addr_len; + /* number of dummy cycles */ + unsigned int pad_cnt; + /* protocol for transmitting command */ + unsigned int cmd_proto; + /* protocol for transmitting address and padding */ + unsigned int addr_proto; + /* protocol for receiving data bytes */ + unsigned int data_proto; + /* value of command byte */ + unsigned int cmd_code; + /* first 8 bits to transmit during dummy cycles */ + unsigned int pad_code; +}; + +int fu540_spi_mmap( + const struct spi_slave *slave, + const struct fu540_spi_mmap_config *config); + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c new file mode 100644 index 0000000..b39a2fe --- /dev/null +++ b/src/soc/sifive/fu540/spi.c @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/spi.h> +#include <soc/clock.h> +#include <soc/addressmap.h> + +#include "spi_internal.h" + +static struct spi_ctrl *spictrls[] = { + (struct spi_ctrl *)FU540_QSPI0, + (struct spi_ctrl *)FU540_QSPI1, + (struct spi_ctrl *)FU540_QSPI2 +}; + + +/** + * Wait until SPI is ready for transmission and transmit byte. + */ +static void spi_tx(volatile struct spi_ctrl *spictrl, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl->txdata.raw_bits < 0) + ; + spictrl->txdata.data = in; +#endif +} + + +/** + * Wait until SPI receive queue has data and read byte. + */ +static uint8_t spi_rx(volatile struct spi_ctrl *spictrl) +{ + int32_t out; + while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0) + ; + return (uint8_t) out; +} + +static int spi_xfer_(const struct spi_slave *slave, + const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + struct spi_ctrl *spictrl = spictrls[slave->cs]; + while (bytesout || bytesin) { + if (bytesout) { + spi_tx(spictrl, *(uint8_t *)dout++); + bytesout--; + } + if (bytesin) { + *(uint8_t *)din++ = spi_rx(spictrl); + bytesin--; + } + } + return 0; +} + +static int spi_setup_(const struct spi_slave *slave) +{ + if ((slave->cs > 2) || (slave->bus != 0)) + return -1; + + struct spi_ctrl *spictrl = spictrls[slave->cs]; + + spictrl->sckdiv = spi_min_clk_divisor(clock_get_tlclk_khz(), 10000); + + spictrl->sckmode.pha = FU540_SPI_PHA_LOW; + spictrl->sckmode.pol = FU540_SPI_POL_LEADING; + + spictrl->csmode.mode = FU540_SPI_CSMODE_AUTO; + + spictrl->fmt.proto = FU540_SPI_PROTO_S; + spictrl->fmt.endian = FU540_SPI_ENDIAN_BIG; + spictrl->fmt.dir = 1; + spictrl->fmt.len = 8; + + return 0; +} + +struct spi_ctrlr fu540_spi_ctrlr = { + .xfer = spi_xfer_, + .setup = spi_setup_, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .bus_start = 0, + .bus_end = 0, + .ctrlr = &fu540_spi_ctrlr, + } +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +int fu540_spi_setup(unsigned int bus, unsigned int cs, + struct spi_slave *slave, + struct fu540_spi_config *config) +{ + if ((cs > 2) || (bus != 0)) + return -1; + + if ((config->pha > 1) + || (config->pol > 1) + || (config->protocol > 2) + || (config->endianness > 1) + || (config->bits_per_frame > 8)) + return -1; + + slave->bus = 0; + slave->cs = cs; + slave->ctrlr = &fu540_spi_ctrlr; + + struct spi_ctrl *spictrl = spictrls[slave->cs]; + + spictrl->sckdiv = spi_min_clk_divisor(clock_get_tlclk_khz(), + config->freq / 1000); + + spictrl->sckmode.pha = config->pha; + spictrl->sckmode.pol = config->pol; + + spictrl->csmode.mode = FU540_SPI_CSMODE_AUTO; + + spictrl->fmt.proto = config->protocol; + spictrl->fmt.endian = config->endianness; + spictrl->fmt.dir = 1; + spictrl->fmt.len = config->bits_per_frame; + + return 0; +} + +int fu540_spi_mmap( + const struct spi_slave *slave, + const struct fu540_spi_mmap_config *config) +{ + if (slave->cs > 2) + return -1; + + if ((config->cmd_en > 1) + || (config->addr_len > 4) + || (config->pad_cnt > 15) + || (config->cmd_proto > 2) + || (config->addr_proto > 2) + || (config->data_proto > 2) + || (config->cmd_code > 255) + || (config->pad_code > 255)) + return -1; + + struct spi_ctrl *spictrl = spictrls[slave->cs]; + + spictrl->fctrl.en = 0; + + spictrl->ffmt.cmd_en = config->cmd_en; + spictrl->ffmt.addr_len = config->addr_len; + spictrl->ffmt.pad_cnt = config->pad_cnt; + spictrl->ffmt.command_proto = config->cmd_proto; + spictrl->ffmt.addr_proto = config->addr_proto; + spictrl->ffmt.data_proto = config->data_proto; + spictrl->ffmt.command_code = config->cmd_code; + spictrl->ffmt.pad_code = config->pad_code; + + spictrl->fctrl.en = 1; + + return 0; +} diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h new file mode 100644 index 0000000..97094c1 --- /dev/null +++ b/src/soc/sifive/fu540/spi_internal.h @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ + +#include <stdint.h> + +#define _ASSERT_SIZEOF(type, size) _Static_assert( \ + sizeof(type) == (size), \ + #type " must be " #size " bytes wide") + +#define FU540_SPI_CSMODE_AUTO 0 +#define FU540_SPI_CSMODE_HOLD 2 +#define FU540_SPI_CSMODE_OFF 3 + +typedef union { + struct { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_sckmode; +_ASSERT_SIZEOF(spi_reg_sckmode, 4); + + +typedef union { + struct { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_csmode; +_ASSERT_SIZEOF(spi_reg_csmode, 4); + + +typedef union { + struct { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay0; +_ASSERT_SIZEOF(spi_reg_delay0, 4); + + +typedef union { + struct { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay1; +_ASSERT_SIZEOF(spi_reg_delay1, 4); + + +typedef union { + struct { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +} spi_reg_fmt; +_ASSERT_SIZEOF(spi_reg_fmt, 4); + + +typedef union { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +} spi_reg_txdata; +_ASSERT_SIZEOF(spi_reg_txdata, 4); + + +typedef union { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +} spi_reg_rxdata; +_ASSERT_SIZEOF(spi_reg_rxdata, 4); + + +typedef union { + struct { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_txmark; +_ASSERT_SIZEOF(spi_reg_txmark, 4); + + +typedef union { + struct { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_rxmark; +_ASSERT_SIZEOF(spi_reg_rxmark, 4); + + +typedef union { + struct { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +} spi_reg_fctrl; +_ASSERT_SIZEOF(spi_reg_fctrl, 4); + + +typedef union { + struct { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t command_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t command_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +} spi_reg_ffmt; +_ASSERT_SIZEOF(spi_reg_ffmt, 4); + + +typedef union { + struct { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_ie; +typedef spi_reg_ie spi_reg_ip; +_ASSERT_SIZEOF(spi_reg_ie, 4); +_ASSERT_SIZEOF(spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +struct spi_ctrl { + uint32_t sckdiv; + spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + spi_reg_delay0 delay0; + spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + spi_reg_fmt fmt; + uint32_t reserved44; + spi_reg_txdata txdata; + spi_reg_rxdata rxdata; + + spi_reg_txmark txmark; + spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + spi_reg_ie ie; + spi_reg_ip ip; +}; + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int +spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not + // exceed max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not + // exceed 2^32 - 1, which is unlikely since we represent frequencies + // in kHz. + unsigned int quotient = + (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9 Gerrit-Change-Number: 33055 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

3 31

Change in ...coreboot[master]: Get rid of PRIu64
by HAOUAS Elyes (Code Review) 10 Aug '19

10 Aug '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33823 Change subject: Get rid of PRIu64 ...................................................................... Get rid of PRIu64 Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/stdint.h M src/arch/arm64/include/stdint.h M src/arch/riscv/include/stdint.h M src/arch/x86/include/stdint.h M src/lib/timestamp.c M util/cbfstool/rmodule.c 6 files changed, 2 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/33823/1 diff --git a/src/arch/arm/include/stdint.h b/src/arch/arm/include/stdint.h index ede0ec9..ae5ff22 100644 --- a/src/arch/arm/include/stdint.h +++ b/src/arch/arm/include/stdint.h @@ -101,9 +101,6 @@ #ifndef UINT64_C #define UINT64_C(c) c ## ULL #endif -#ifndef PRIu64 -#define PRIu64 "llu" -#endif #undef __HAVE_LONG_LONG__ diff --git a/src/arch/arm64/include/stdint.h b/src/arch/arm64/include/stdint.h index cb07a07..e40a9f5 100644 --- a/src/arch/arm64/include/stdint.h +++ b/src/arch/arm64/include/stdint.h @@ -79,8 +79,5 @@ #ifndef UINT64_MAX # define UINT64_MAX (18446744073709551615ULL) #endif -#ifndef PRIu64 -#define PRIu64 "llu" -#endif #endif /* ARM64_STDINT_H */ diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h index 76f0d1b..eaaba18 100644 --- a/src/arch/riscv/include/stdint.h +++ b/src/arch/riscv/include/stdint.h @@ -73,7 +73,4 @@ typedef long intptr_t; typedef unsigned long uintptr_t; -/* FIXME: This is used in some print code and may be removed in the future. */ -#define PRIu64 "llu" - #endif /* RISCV_STDINT_H */ diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index 6c40002..262c6a3 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -102,11 +102,6 @@ #ifndef UINT64_C #define UINT64_C(c) c ## ULL #endif -#ifndef PRIu64 -#define PRIu64 "llu" - -#endif - #undef __HAVE_LONG_LONG__ diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index adacf6b..347e937 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -180,7 +180,7 @@ tse->entry_stamp = ts_time - ts_table->base_time; if (CONFIG(TIMESTAMPS_ON_CONSOLE)) - printk(BIOS_SPEW, "Timestamp - %s: %" PRIu64 "\n", + printk(BIOS_SPEW, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); if (ts_table->num_entries == ts_table->max_entries) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 80e8911..c1fcd13 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -328,7 +328,7 @@ return -1; nrelocs = ctx->nrelocs; - INFO("%" PRIu64 " relocations to be emitted.\n", nrelocs); + INFO("%llu relocations to be emitted.\n", nrelocs); if (!nrelocs) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14 Gerrit-Change-Number: 33823 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

8 60

Change in ...coreboot[master]: _WIP_ soc/amd/picasso: Update i2c support
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33763 Change subject: _WIP_ soc/amd/picasso: Update i2c support ...................................................................... _WIP_ soc/amd/picasso: Update i2c support * todo: pad config Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 7 files changed, 43 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33763/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cdb32cc..355fbeb 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -48,12 +48,11 @@ TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max Offset (0x34), // 0x34 - AOAC Device Enables - , 5, - IC0E, 1, // I2C0, 5 - IC1E, 1, // I2C1, 6 + , 7, IC2E, 1, // I2C2, 7 IC3E, 1, // I2C3, 8 - , 2, + IC4E, 1, // I2C4, 9 + , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 , 2, diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8cdb4d2..1d8768b 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -530,16 +530,6 @@ FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { - FDDC(5, 3) - } - } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { - FDDC(6, 3) - } - } if(LEqual(\IC2E, zero)) { if(LNotEqual(I2TD, 0x03)) { FDDC(7, 3) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 9fe1588..27d7885 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -25,25 +25,21 @@ #include <soc/i2c.h> #include "chip.h" -#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) - /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); static const uintptr_t i2c_bus_address[] = { - I2CA_BASE_ADDRESS, - I2CB_BASE_ADDRESS, - I2CC_BASE_ADDRESS, - I2CD_BASE_ADDRESS, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* slave device only */ }; uintptr_t dw_i2c_base_address(unsigned int bus) { - return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + return 0; + + return i2c_bus_address[bus - APU_I2C_MIN_BUS]; } static const struct soc_amd_picasso_config *get_soc_config(void) @@ -63,7 +59,7 @@ { const struct soc_amd_picasso_config *config; - if (bus >= ARRAY_SIZE(i2c_bus_address)) + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) return NULL; config = get_soc_config(); @@ -76,14 +72,12 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return "I2CA"; - case I2CB_BASE_ADDRESS: - return "I2CB"; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return "I2CC"; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return "I2CD"; + case APU_I2C4_BASE: + return "I2CE"; default: return NULL; } @@ -92,18 +86,17 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return 0; - case I2CB_BASE_ADDRESS: - return 1; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return 2; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return 3; + case APU_I2C4_BASE: + return 4; } return -1; } +/* TODO: MISC::I2C[n]_PadCtrl may require programming */ static void dw_i2c_soc_init(bool is_early_init) { size_t i; @@ -152,10 +145,9 @@ * conversion of all SCL pins to input with no pull. */ static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), PAD_GPI(I2C2_SCL_PIN, PULL_NONE), PAD_GPI(I2C3_SCL_PIN, PULL_NONE), + /* I2C4 is a slave device only */ }; #define saved_pins_count ARRAY_SIZE(i2c_2_gpi) @@ -210,10 +202,6 @@ * needed after the writes to force the posted write to complete. */ for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) @@ -222,10 +210,6 @@ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index fb9b113..d129fc1 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -23,24 +23,18 @@ uint8_t mux_value; }; -#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(2) | BIT(3)) -#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 -#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) #define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) #define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) +#define GPIO_SCL_HIGH 0 +#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE -#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1d89fd7..b9d1ab5 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -43,9 +43,16 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 +#define APU_I2C4_BASE 0xfedc6000 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_DEVICE_COUNT 3 + #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6733946..04e9a25 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -180,10 +180,9 @@ /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c #define FCH_AOAC_D3_CONTROL_I2C2 0x4e #define FCH_AOAC_D3_CONTROL_I2C3 0x50 +#define FCH_AOAC_D3_CONTROL_I2C4 0x52 #define FCH_AOAC_D3_CONTROL_UART0 0x56 #define FCH_AOAC_D3_CONTROL_UART1 0x58 #define FCH_AOAC_D3_CONTROL_AMBA 0x62 @@ -199,10 +198,9 @@ #define FCH_AOAC_IS_SW_CONTROL BIT(7) #define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d #define FCH_AOAC_D3_STATE_I2C2 0x4f #define FCH_AOAC_D3_STATE_I2C3 0x51 +#define FCH_AOAC_D3_STATE_I2C4 0x53 #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 @@ -290,12 +288,11 @@ }; typedef struct aoac_devs { - unsigned int :5; - unsigned int ic0e:1; /* 5: I2C0 */ - unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int :2; + unsigned int ic4e:1; /* 9: I2C4 */ + unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index d0e12a9..f487d08 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -46,10 +46,9 @@ { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } + { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }, + { FCH_AOAC_D3_CONTROL_I2C4, FCH_AOAC_D3_STATE_I2C4 } }; /* @@ -528,10 +527,9 @@ if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C4); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); /* Rely on these being in sync with devicetree */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Gerrit-Change-Number: 33763 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: soc/amd/picasso: Reduce 48M out configuration
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33768 Change subject: soc/amd/picasso: Reduce 48M out configuration ...................................................................... soc/amd/picasso: Reduce 48M out configuration Picasso has only a single 48M output. Simplify the setup function. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 --- M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 2 files changed, 4 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/33768/1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 04e9a25..4a7f730 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -175,8 +175,7 @@ #define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) -#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ -#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ +#define BP_X48M0_OUTPUT_EN BIT(2) /* 0 = Enabled, 1 = Disabled */ /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 @@ -313,7 +312,7 @@ }; void enable_aoac_devices(void); -void sb_clk_output_48Mhz(u32 osc); +void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index f487d08..f1616ab 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -189,26 +189,12 @@ pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); } -void sb_clk_output_48Mhz(u32 osc) +void sb_clk_output_48Mhz(void) { u32 ctrl; - /* - * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) - * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. - */ ctrl = misc_read32(MISC_CLK_CNTL1); - - switch (osc) { - case 1: - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; - break; - case 2: - ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; - break; - default: - return; /* do nothing if invalid */ - } + ctrl |= BP_X48M0_OUTPUT_EN; misc_write32(MISC_CLK_CNTL1, ctrl); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 Gerrit-Change-Number: 33768 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: soc/amd/picasso: Update SMI souces
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33771 Change subject: soc/amd/picasso: Update SMI souces ...................................................................... soc/amd/picasso: Update SMI souces Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c --- M src/soc/amd/picasso/include/soc/smi.h 1 file changed, 118 insertions(+), 121 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33771/1 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index da32610..66c2050 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -33,128 +33,125 @@ # define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) /* SMI source and status */ -#define SMITYPE_AGPIO65 0 -#define SMITYPE_AGPIO66 1 -#define SMITYPE_AGPIO3 2 -#define SMITYPE_LPCPME_AGPIO22 3 -#define SMITYPE_GPIO4 4 -#define SMITYPE_LPCPD_AGPIOG21 5 -#define SMITYPE_IRTX1_G15 6 -#define SMITYPE_AGPIO5_DEVSLP0 7 -#define SMITYPE_WAKE_AGPIO2 8 -#define SMITYPE_APIO68_SGPIOCLK 9 -#define SMITYPE_AGPIO6 10 -#define SMITYPE_GPIO7 11 -#define SMITYPE_USBOC0_TRST_AGPIO16 12 -#define SMITYPE_USB0C1_TDI_AGPIO17 13 -#define SMITYPE_USBOC2_TCK_AGPIO18 14 -#define SMITYPE_TDO_USB0C3_AGPIO24 15 -#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16 -/* 17 Reserved */ -#define SMITYPE_BLINK_AGPIO11_USBOC7 18 -#define SMITYPE_SYSRESET_AGPIO1 19 -#define SMITYPE_IRRX1_AGPIO15 20 -#define SMITYPE_IRTX0_USBOC5_AGPIO13 21 -#define SMITYPE_GPIO9_SERPORTRX 22 -#define SMITYPE_GPIO8_SEPORTTX 23 -#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \ - | (1 << SMITYPE_AGPIO66) \ - | (1 << SMITYPE_AGPIO3) \ - | (1 << SMITYPE_LPCPME_AGPIO22) \ - | (1 << SMITYPE_GPIO4) \ - | (1 << SMITYPE_LPCPD_AGPIOG21) \ - | (1 << SMITYPE_IRTX1_G15) \ - | (1 << SMITYPE_AGPIO5_DEVSLP0) \ - | (1 << SMITYPE_WAKE_AGPIO2) \ - | (1 << SMITYPE_APIO68_SGPIOCLK) \ - | (1 << SMITYPE_AGPIO6) \ - | (1 << SMITYPE_GPIO7) \ - | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \ - | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \ - | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \ - | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \ - | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \ - | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \ - | (1 << SMITYPE_SYSRESET_AGPIO1) \ - | (1 << SMITYPE_IRRX1_AGPIO15) \ - | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \ - | (1 << SMITYPE_GPIO9_SERPORTRX)) -#define SMITYPE_EHCI0_WAKE 24 -#define SMITYPE_EHCI1_WAKE 25 -#define SMITYPE_ESPI_SYS 26 -#define SMITYPE_ESPI_WAKE_PME 27 -/* 28-32 Reserved */ -#define SMITYPE_FCH_FAKE0 33 -#define SMITYPE_FCH_FAKE1 34 -#define SMITYPE_FCH_FAKE2 35 -/* 36 Reserved */ -#define SMITYPE_SATA_GEVENT0 37 -#define SMITYPE_SATA_GEVENT1 38 -#define SMITYPE_ACP_WAKE 39 -#define SMITYPE_ECG 40 -#define SMITYPE_GPIO_CTL 41 -#define SMITYPE_CIR_PME 42 -#define SMITYPE_ALT_HPET_ALARM 43 -#define SMITYPE_FAN_THERMAL 44 -#define SMITYPE_ASF_MASTER_SLAVE 45 -#define SMITYPE_I2S_WAKE 46 -#define SMITYPE_SMBUS0_MASTER 47 -#define SMITYPE_TWARN 48 -#define SMITYPE_TRAFFIC_MON 49 -#define SMITYPE_ILLB 50 -#define SMITYPE_PWRBUTTON_UP 51 -#define SMITYPE_PROCHOT 52 -#define SMITYPE_APU_HW 53 -#define SMITYPE_NB_SCI 54 -#define SMITYPE_RAS_SERR 55 -#define SMITYPE_XHC0_PME 56 -/* 57 Reserved */ -#define SMITYPE_ACDC_TIMER 58 -/* 59-62 Reserved */ -#define SMITYPE_TEMP_TSI 63 -#define SMITYPE_KB_RESET 64 -#define SMITYPE_SLP_TYP 65 -#define SMITYPE_AL2H_ACPI 66 -#define SMITYPE_AHCI 67 -/* 68-71 Reserved */ -#define SMITYPE_GBL_RLS 72 -#define SMITYPE_BIOS_RLS 73 -#define SMITYPE_PWRBUTTON_DOWN 74 -#define SMITYPE_SMI_CMD_PORT 75 -#define SMITYPE_USB_SMI 76 -#define SMITYPE_SERIRQ 77 -#define SMITYPE_SMBUS0_INTR 78 -#define SMITYPE_XHC_ERROR 80 -#define SMITYPE_INTRUDER 81 -#define SMITYPE_VBAT_LOW 82 -#define SMITYPE_PROTHOT 83 -#define SMITYPE_PCI_SERR 84 -#define SMITYPE_GPP_SERR 85 -/* 85-88 Reserved */ -#define SMITYPE_TMERTRIP 89 -#define SMITYPE_EMUL60_64 90 -#define SMITYPE_USB_FLR 91 -#define SMITYPE_SATA_FLR 92 -#define SMITYPE_AZ_FLR 93 -/* 94-132 Reserved */ -#define SMITYPE_FANIN0 133 -/* 134-137 Reserved */ -#define SMITYPE_FAKE0 138 -#define SMITYPE_FAKE1 139 -#define SMITYPE_FAKE2 140 -/* 141 Reserved */ -#define SMITYPE_SHORT_TIMER 142 -#define SMITYPE_LONG_TIMER 143 -#define SMITYPE_AB_SMI 144 -#define SMITYPE_SOFT_RESET 145 -/* 146-147 Reserved */ -#define SMITYPE_IOTRAP0 148 -/* 149-151 Reserved */ -#define SMITYPE_MEMTRAP0 152 +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_LPCPME 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_LPCPD 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_LPC_SMI_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_ESPI_RESET_L 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_LPCPME) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_LPCPD) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +/* 33 - 38 Reserved */ +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +/* 42 Reserved */ +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-63 Reserved */ +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +#define SMITYPE_AHCI 67 +#define SMITYPE_NB_GPP_PME_PULSE 68 +#define SMITYPE_NB_GPP_HP_PULSE 69 +#define SMITYPE_USBPD_I2C_INT 70 +/* 71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +#define SMITYPE_GPP_SERR 85 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 /* 153-155 Reserved */ -#define SMITYPE_CFGTRAP0 156 +#define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 +#define NUMBER_SMITYPES 160 #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 -- To view, visit https://review.coreboot.org/c/coreboot/+/33771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c Gerrit-Change-Number: 33771 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Update machine check support
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33769 Change subject: soc/amd/picasso: Update machine check support ...................................................................... soc/amd/picasso: Update machine check support Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f --- M src/soc/amd/picasso/mca.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33769/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 8a875d9..57fa9c6 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -97,11 +97,6 @@ * which is the best method to report MSR context. As a result, add two * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. */ static void build_bert_mca_error(struct mca_bank *mci) { @@ -161,6 +156,7 @@ "Floating point unit" }; +/* Check the Legacy Machine Check Architecture registers */ void check_mca(void) { int i; @@ -173,9 +169,6 @@ if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; -- To view, visit https://review.coreboot.org/c/coreboot/+/33769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f Gerrit-Change-Number: 33769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: _WIP_ soc/amd/common: Add new GPIO pull-up definition
by Marshall Dawson (Code Review) 09 Aug '19

09 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33762 Change subject: _WIP_ soc/amd/common: Add new GPIO pull-up definition ...................................................................... _WIP_ soc/amd/common: Add new GPIO pull-up definition todo: incorporate into a macro? Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a --- M src/soc/amd/common/block/include/amdblocks/gpio_banks.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33762/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index da84134..a415d35 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -59,6 +59,7 @@ #define GPIO_S4_S5_WAKE_EN (1 << 15) #define GPIO_PIN_STS (1 << 16) +#define GPIO_8KPULLUP_SELECT (1 << 19) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) #define GPIO_OUTPUT_SHIFT 22 -- To view, visit https://review.coreboot.org/c/coreboot/+/33762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a Gerrit-Change-Number: 33762 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019