coreboot-gerrit June 2019

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Change in ...coreboot[master]: soc/mediatek: Register coreboot table for ATF
by Hung-Te Lin (Code Review) 05 Sep '19

05 Sep '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32541 Change subject: soc/mediatek: Register coreboot table for ATF ...................................................................... soc/mediatek: Register coreboot table for ATF Register coreboot table into BL31 parameter so ATF can find coreboot information and use it (for example, use memory console). BUG=None TEST=emerge-kukui coreboot; Boots on Kukui. Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/bl31_plat_params.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32541/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c index eb7477a..51edab3 100644 --- a/src/soc/mediatek/common/bl31_plat_params.c +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -14,6 +14,7 @@ */ #include <arm_tf.h> +#include <cbmem.h> #include <soc/bl31_plat_params.h> static struct bl31_plat_param *plat_params; @@ -26,5 +27,13 @@ void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) { + static struct bl31_u64_param cbtable_param = { + .h = { .type = PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_param(&cbtable_param.h); + } return plat_params; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Gerrit-Change-Number: 32541 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for has...
by Frans Hendriks (Code Review) 04 Sep '19

04 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33251 Change subject: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size ...................................................................... security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size mashal_TPMT_HA() uses size of SHA-256 hash. Use tlcll_get_hash_size_from_algo(0) to determince the hash size. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33251/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 548a39a..2ff9eed 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -70,6 +70,14 @@ * custom tpm standards like cr50 */ void *tpm_process_command(TPM_CC command, void *command_body); +/* + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); #endif diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..24d7726 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -361,3 +361,33 @@ return TPM_SUCCESS; } +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t value; + + switch (hashAlgo) { + case TPM_ALG_ERROR: + value = 1; + break; + case TPM_ALG_SHA1: + value = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + value = SHA256_DIGEST_SIZE; + break; + default: + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + value = 0; + }; + + return value; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 21da73a..a74eb09 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -12,6 +12,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +83,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..dcd4468 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -36,12 +36,24 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ +/* Table 7 - TPM_ALG_ID Constants */ +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) #define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) #define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) #define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) #define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +/* Annex A Algorithm Constants */ + +/* Table 205 - Defines for SHA1 Hash Values */ +#define SHA1_DIGEST_SIZE 20 +/* Table 206 - Defines for SHA256 Hash Values */ #define SHA256_DIGEST_SIZE 32 +/* Table 208 - Defines for SHA512 Hash Values */ +#define SHA512_DIGEST_SIZE 64 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 -- To view, visit https://review.coreboot.org/c/coreboot/+/33251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Gerrit-Change-Number: 33251 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/quark: Remove variable set but not used
by HAOUAS Elyes (Code Review) 02 Sep '19

02 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32912 Change subject: soc/intel/quark: Remove variable set but not used ...................................................................... soc/intel/quark: Remove variable set but not used Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/quark/i2c.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32912/1 diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818..49ebaa2 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -117,7 +117,6 @@ int bytes_transferred; uint32_t cmd; int fifo_bytes; - uint8_t junk; I2C_REGS *regs; uint32_t status; @@ -128,7 +127,7 @@ /* Empty the FIFO */ status = regs->ic_status; while (status & IC_STATUS_RFNE) { - junk = (uint8_t)regs->ic_data_cmd; + (uint8_t)regs->ic_data_cmd; status = regs->ic_status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Gerrit-Change-Number: 32912 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in ...coreboot[master]: ec/kontron/kempld: Select DRIVERS_UART_8250IO
by Thomas Heijligen (Code Review) 02 Sep '19

02 Sep '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31366 to review the following change. Change subject: ec/kontron/kempld: Select DRIVERS_UART_8250IO ...................................................................... ec/kontron/kempld: Select DRIVERS_UART_8250IO Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/ec/kontron/kempld/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31366/1 diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig index 647bd12..08401c9 100644 --- a/src/ec/kontron/kempld/Kconfig +++ b/src/ec/kontron/kempld/Kconfig @@ -1,5 +1,6 @@ config EC_KONTRON_KEMPLD bool + select DRIVERS_UART_8250IO help Driver for Kontron's express module programmable logic device used on their COMexpress modules. -- To view, visit https://review.coreboot.org/c/coreboot/+/31366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Gerrit-Change-Number: 31366 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in ...libgfxinit[master]: gma display_probing: End probing after all ports failed
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32728 Change subject: gma display_probing: End probing after all ports failed ...................................................................... gma display_probing: End probing after all ports failed In case of failure, we kept trying the last port in the list for further pipelines. Fix that. Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/28/32728/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index cd2a452..d21b277 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -183,6 +184,7 @@ for Pipe in Pipe_Index range Pipe_Index'First .. Pipe_Index'Min (Max_Pipe, Config.Max_Pipe) loop + Success := False; while Ports (Port_Idx) /= Disabled loop if not Port_Configured (Configs, Ports (Port_Idx)) and (not Has_Sibling_Port (Ports (Port_Idx)) or @@ -198,6 +200,7 @@ exit when Success; end loop; + exit when not Success; end loop; -- Restore power settings -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Gerrit-Change-Number: 32728 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: mb/*: Use common IPMI KCS driver
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33490 Change subject: mb/*: Use common IPMI KCS driver ...................................................................... mb/*: Use common IPMI KCS driver Remove duplicated code and instead use the IPMI KCS driver, which provides the same functionality. Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c 8 files changed, 7 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33490/1 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 32c4dbc..64beaf0 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -33,6 +33,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select POWER_STATE_DEFAULT_ON_AFTER_FAILURE + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..31bd3e3 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -217,7 +217,7 @@ chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end - chip drivers/generic/generic # BMC KCS + chip drivers/ipmi # BMC KCS device pnp ca2.0 on end end end diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ea52488..efb67a5 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -53,9 +53,6 @@ #include <southbridge/amd/common/acpi/sleepstates.asl> - /* IPMI KCS enable */ - Name (KCSE, 0x1) - /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * @@ -489,13 +486,6 @@ Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - OperationRegion (BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */ - Field (BMRG, AnyAcc, NoLock, Preserve) - { - BMRI, 8, /* Index */ - BMRD, 8, /* Data */ - } - /* Real Time Clock Device */ Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ @@ -617,27 +607,6 @@ }) } } - - Device (KCS1) { /* IPMI KCS */ - Name (_HID, EISAID ("IPI0001")) /* ASpeed BMC */ - Method (_STA, 0, NotSerialized) { - If (KCSE) { /* Detection enabled */ - If (LNotEqual (BMRD, 0xff)) { - Return (0x0f) /* Device present */ - } - Return (Zero) - } - Return (Zero) - } - Method (_CRS, 0) { - Return (ResourceTemplate() { - IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02) - }) - } - Method (_IFT, 0, NotSerialized) { /* Interface type */ - Return (One) /* KCS interface */ - } - } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 14bb986..a03953b 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -47,7 +47,6 @@ * enable the dedicated function in kgpe-d16 board. * This function is called earlier than sr5650_enable. *************************************************/ -#define BMC_KCS_BASE 0xca2 static void mainboard_enable(struct device *dev) { @@ -69,13 +68,6 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /* override the default SATA PHY setup */ diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 037c322..7af4ae9 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select IPMI_KCS config INTEGRATED_UART def_bool n diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 2d91b73..5b990db 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -11,8 +11,10 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end - chip drivers/generic/generic # BMC KCS - device pnp ca2.0 on end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on + register "bmc_i2c_address" = "0x20" + end end end # LPC Bridge device pci 1f.2 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 72b1c3c..1248703 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,9 +27,6 @@ { #include "acpi/platform.asl" - Name (IDTP, 0x0CA2) - Name (ICDP, 0x0CA6) - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -293,97 +290,5 @@ } } - Scope (_SB.PCI0.LPC0) - { - Device (SPMI) - { - Name (_HID, EisaId ("IPI0001")) - Name (_STR, Unicode ("IPMI_KCS")) - Name (_UID, 0x00) - OperationRegion (IPST, SystemIO, ICDP, 0x01) - Field (IPST, ByteAcc, NoLock, Preserve) - { - STAS, 8 - } - Method (_STA, 0, NotSerialized) { - Return (0x0f) - } - Name (ICRS, ResourceTemplate () - { - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y01) - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y02) - - }) - Method (_CRS, 0, NotSerialized) - { - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) - - IPDB = IDTP - IPDH = IDTP - IPDL = 0x01 - - IPCB = ICDP - IPCH = ICDP - IPCL = 0x01 - - Return (ICRS) - } - Method (_IFT, 0, NotSerialized) { - Return (0x01) - } - Method(_SRV, 0, NotSerialized) { - Return (0x0200) - } - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0CA2, - 0x0CA2, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA6, - 0x0CA6, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA8, - 0x0CA8, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CAC, - 0x0CAC, - 0x01, - 0x01, - ) - }) - } - } - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index bbfeeaf..4395436 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -20,46 +20,12 @@ #include <x86emu/x86emu.h> #endif -#define BMC_KCS_BASE 0xca2 -#define INTERFACE_IS_IO 0x1 - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - int len = 0; - - // add IPMI Device Information - len += smbios_write_type38( - current, handle, - SMBIOS_BMC_INTERFACE_KCS, - 0x20, // IPMI Version - 0x20, // I2C address - 0xff, // no NV storage - BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address - 0x40, - 0); // no IRQ - - return len; -} -#endif - /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Gerrit-Change-Number: 33490 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/buddy: adjust CID for realtek audio codec
by Matt DeVillier (Code Review) 30 Aug '19

30 Aug '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30564 Change subject: google/buddy: adjust CID for realtek audio codec ...................................................................... google/buddy: adjust CID for realtek audio codec Adjust CID to allow for Windows driver to attach without breaking functionality under Linux. Same change made as to google/cyan (which uses same Realtek RT5650 codec) in commit 607d72b. Test: build/boot Windowns 10 on google/buddy, observe audio drivers correctly attached to codec and Intel SST devices. Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30564/1 diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc..f4ed69e 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -19,7 +19,7 @@ Device (RTEK) { Name (_HID, "10EC5650") - Name (_CID, "10EC5650") + Name (_CID, "INTCCFFD") Name (_DDN, "RTEK Codec Controller ") Name (_UID, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/30564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Gerrit-Change-Number: 30564 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: arch/arm: Make ARM specific options depend on select ARCH_ARM
by Arthur Heymans (Code Review) 29 Aug '19

29 Aug '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31313 Change subject: arch/arm: Make ARM specific options depend on select ARCH_ARM ...................................................................... arch/arm: Make ARM specific options depend on select ARCH_ARM Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig 8 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31313/1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 6d9cc78..14d054a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,11 +1,11 @@ config ARCH_ARM bool - default n + +if ARCH_ARM config ARCH_BOOTBLOCK_ARM bool default n - select ARCH_ARM select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM @@ -26,3 +26,5 @@ config ARM_LPAE bool default n + +endif #if ARCH_ARM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index eecb59b..e9e43a5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA124 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV7 diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 8883baa..52118c3 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA210 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV4 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05fa..7a0648c 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ40XX bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0b112d9..3bea529 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ806X bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 53666c2..654374c 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -16,6 +16,7 @@ config SOC_ROCKCHIP_RK3288 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 5b39724..149d703 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5250 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7b87650..4ffbf7f 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5420 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Gerrit-Change-Number: 31313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 27 Aug '19

27 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30901 Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc D src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/include/soc/sd.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/sd.c 8 files changed, 490 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30901/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 2dac283..54d97f7 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,12 +11,26 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += memlayout.ld bootblock-y += flash.c -bootblock-y += bootblock.c +bootblock-y += media.c +romstage-y += memlayout.ld romstage-y += flash.c +romstage-y += media.c romstage-y += romstage.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld ramstage-y += memlayout.ld +ramstage-y += flash.c +ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw + diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c deleted file mode 100644 index 777b2aa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/bootblock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/spi.h> -#include <soc/spi_flash.h> -#include <soc/clock.h> - -extern void flash_init(void); -extern void bootblock_mainboard_init(void); - -void bootblock_mainboard_init(void) -{ - flash_init(); -} diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..4a8f463 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/sd.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> + +void flash_init(void); +// void boot_device_init(void); +// const struct region_device *boot_device_ro(void); + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device spi_mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + if (offset / 512 == (offset + count - 1) / 512) { + size_t lba = offset / 512; + size_t o = offset % 512; + size_t l = count; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } else { + int has_begin = !!(offset % 512); + int has_end = !!((offset + count) % 512); + size_t first_lba = offset / 512; + size_t last_lba = (offset + count - 1) / 512; + if (has_begin) { + size_t lba = first_lba; + size_t o = offset % 512; + size_t l = 512 - o; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } + if (first_lba + has_begin <= last_lba - has_end) { + size_t lba = first_lba + has_begin; + size_t size = (last_lba - has_end) - (first_lba + has_begin) + 1; + size_t o = 512 - offset % 512; + if (sd_copy((spi_ctrl*)FU540_QSPI2, dest + o, lba, size) != 0) { + return -1; + } + } + if (has_end) { + size_t lba = last_lba; + size_t o = 0; + size_t l = (offset + count) % 512; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest + count - l, tmp + o, l); + } + } + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + + +const struct region_device *boot_device_ro() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; +} + +void boot_device_init() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + flash_init(); + break; + case 11: + sd_init((spi_ctrl*)FU540_QSPI2, clock_get_tlclk_khz()); + mmap_helper_device_init(&sd_mdev, _cbfs_cache, _cbfs_cache_size); + break; + default: + die("Wrong configuration of MSEL"); + } +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 83c7b1c..866267e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,28 +15,31 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +# bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += spi.c +bootblock-y += sd.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +# romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c romstage-y += spi.c +romstage-y += sd.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +# ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sd.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } diff --git a/src/soc/sifive/fu540/include/soc/sd.h b/src/soc/sifive/fu540/include/soc/sd.h new file mode 100644 index 0000000..679d0f4 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/sd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _LIBRARIES_SD_H +#define _LIBRARIES_SD_H + +#define SD_INIT_ERROR_CMD0 1 +#define SD_INIT_ERROR_CMD8 2 +#define SD_INIT_ERROR_ACMD41 3 +#define SD_INIT_ERROR_CMD58 4 +#define SD_INIT_ERROR_CMD16 5 + +#define SD_COPY_ERROR_CMD18 1 +#define SD_COPY_ERROR_CMD18_CRC 2 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +int sd_init(spi_ctrl* spi, unsigned int input_clk_hz); +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size); + +#endif /* !__ASSEMBLER__ */ + +#endif /* _LIBRARIES_SD_H */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/sd.c b/src/soc/sifive/fu540/sd.c new file mode 100644 index 0000000..3af26ad --- /dev/null +++ b/src/soc/sifive/fu540/sd.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/spi.h> +#include <soc/sd.h> + + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SD_CMD_GO_IDLE_STATE 0 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_CMD 55 +#define SD_CMD_READ_OCR 58 +#define SD_RESPONSE_IDLE 0x1 +// Data token for commands 17, 18, 24 +#define SD_DATA_TOKEN 0xfe + + +// SD card initialization must happen at 100-400kHz +#define SD_POWER_ON_FREQ_KHZ 400L +// SD cards normally support reading/writing at 20MHz +#define SD_POST_INIT_CLK_KHZ 20000L + + +// Command frame starts by asserting low and then high for first two clock edges +#define SD_CMD(cmd) (0x40 | (cmd)) + + +/** + * Send dummy byte (all ones). + * + * Used in many cases to read one byte from SD card, since SPI is a full-duplex + * protocol and it is necessary to send a byte in order to read a byte. + */ +static inline uint8_t sd_dummy(spi_ctrl* spi) +{ + return spi_txrx(spi, 0xFF); +} + + +static int sd_cmd(spi_ctrl* spi, uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + spi->csmode.mode = SPI_CSMODE_HOLD; + sd_dummy(spi); + spi_txrx(spi, cmd); + spi_txrx(spi, arg >> 24); + spi_txrx(spi, arg >> 16); + spi_txrx(spi, arg >> 8); + spi_txrx(spi, arg); + spi_txrx(spi, crc); + + n = 1000; + do { + r = sd_dummy(spi); + if (!(r & 0x80)) { + break; + } + } while (--n > 0); + return r; +} + + +static inline void sd_cmd_end(spi_ctrl* spi) +{ + sd_dummy(spi); + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(spi_ctrl* spi, unsigned int input_clk_khz) +{ + // Initialize SPI controller + spi->fmt.raw_bits = ((spi_reg_fmt) { + .proto = SPI_PROTO_S, + .dir = SPI_DIR_RX, + .endian = SPI_ENDIAN_MSB, + .len = 8, + }).raw_bits; + spi->csdef |= 0x1; + spi->csid = 0; + + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POWER_ON_FREQ_KHZ); + spi->csmode.mode = SPI_CSMODE_OFF; + + for (int i = 10; i > 0; i--) { + // Set SD card pin DI high for 74+ cycles + // SD CMD pin is the same pin as SPI DI, so CMD = 0xff means assert DI high + // for 8 cycles. + sd_dummy(spi); + } + + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +/** + * Reset card. + */ +static int sd_cmd0(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_GO_IDLE_STATE), 0, 0x95) != SD_RESPONSE_IDLE); + sd_cmd_end(spi); + return rc; +} + + +/** + * Check for SD version and supported voltages. + */ +static int sd_cmd8(spi_ctrl* spi) +{ + // Check for high capacity cards + // Fail if card does not support SDHC + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SEND_IF_COND), 0x000001AA, 0x87) != SD_RESPONSE_IDLE); + sd_dummy(spi); /* command version; reserved */ + sd_dummy(spi); /* reserved */ + rc |= ((sd_dummy(spi) & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy(spi) != 0xAA); /* check pattern */ + sd_cmd_end(spi); + return rc; +} + + +/** + * Send app command. Used as prefix to app commands (ACMD). + */ +static void sd_cmd55(spi_ctrl* spi) +{ + sd_cmd(spi, SD_CMD(SD_CMD_APP_CMD), 0, 0x65); + sd_cmd_end(spi); +} + + +/** + * Start SDC initialization process. + */ +static int sd_acmd41(spi_ctrl* spi) +{ + uint8_t r; + do { + sd_cmd55(spi); + r = sd_cmd(spi, SD_CMD(SD_CMD_APP_SEND_OP_COND), 0x40000000, 0x77); /* HCS = 1 */ + sd_cmd_end(spi); + } while (r == SD_RESPONSE_IDLE); + return (r != 0x00); +} + + +/** + * Read operation conditions register (OCR) to check for availability of block + * addressing mode. + */ +static int sd_cmd58(spi_ctrl* spi) +{ + // HACK: Disabled due to bugs. It is not strictly necessary + // to issue this command if we only support SD cards that support SDHC mode. + return 0; + // int rc; + // rc = (sd_cmd(spi, SD_CMD(SD_CMD_READ_OCR), 0, 0xFD) != 0x00); + // rc |= ((sd_dummy(spi) & 0x80) != 0x80); /* Power up status */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_cmd_end(spi); + // return rc; +} + + +/** + * Set block addressing mode. + */ +static int sd_cmd16(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SET_BLOCKLEN), 0x200, 0x15) != 0x00); + sd_cmd_end(spi); + return rc; +} + + +static uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + + +static uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + + +//int sd_init(spi_ctrl* spi, unsigned int input_clk_khz, int skip_sd_init_commands) +int sd_init(spi_ctrl* spi, unsigned int input_clk_khz) +{ + sd_poweron(spi, input_clk_khz); + if (sd_cmd0(spi)) + return SD_INIT_ERROR_CMD0; + if (sd_cmd8(spi)) + return SD_INIT_ERROR_CMD8; + if (sd_acmd41(spi)) + return SD_INIT_ERROR_ACMD41; + if (sd_cmd58(spi)) + return SD_INIT_ERROR_CMD58; + if (sd_cmd16(spi)) + return SD_INIT_ERROR_CMD16; + + // Increase clock frequency after initialization for higher performance. + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POST_INIT_CLK_KHZ); + return 0; +} + + +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t c = 0; + c = crc7(c, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE)); + c = crc7(c, src_lba >> 24); + c = crc7(c, (src_lba >> 16) & 0xff); + c = crc7(c, (src_lba >> 8) & 0xff); + c = crc7(c, src_lba & 0xff); + c = (c << 1) | 1; + if (sd_cmd(spi, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE), src_lba, c) != 0x00) { + sd_cmd_end(spi); + return SD_COPY_ERROR_CMD18; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy(spi) != SD_DATA_TOKEN); + do { + uint8_t x = sd_dummy(spi); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy(spi) << 8); + crc_exp |= sd_dummy(spi); + + if (crc != crc_exp) { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + } while (--i > 0); + + sd_cmd(spi, SD_CMD(SD_CMD_STOP_TRANSMISSION), 0, 0x01); + sd_cmd_end(spi); + return rc; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Gerrit-Change-Number: 30901 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG
by You-Cheng Syu (Code Review) 26 Aug '19

26 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31844 Change subject: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG ...................................................................... google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG so that it will query the reset reason from EC during watchdog initialization. Besides, we should set BOOTBLOCK_EN_L before mtk_wdt_init so that we can communicate with EC at the time. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. see 'WDT: Last reset was hardware watchdog' in AP console 4. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/early_init.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31844/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..4d4feac 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -33,6 +33,7 @@ select FATAL_ASSERTS select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..9495af3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -25,11 +25,11 @@ void mainboard_early_init(void) { - mt8183_early_init(); - /* Turn on real eMMC and allow communication to EC. */ gpio_output(BOOTBLOCK_EN_L, 1); + mt8183_early_init(); + setup_chromeos_gpios(); /* Declare we are in S0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Gerrit-Change-Number: 31844 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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