coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/google/glados: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32741 Change subject: mb/google/glados: Fix false coverity alarms ...................................................................... mb/google/glados: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. As simply replicating the memcpy() calls doesn't make the code any more readable, use the new memcpy_elen() and memcpy_dlen() macros. CID=1401338..1401340, 1401342..1401343 Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/variant.c 7 files changed, 50 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32741/1 diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4c77897..1800470a 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> void variant_memory_init_params( MEMORY_INIT_UPD *const memory_params, const int spd_index) @@ -39,14 +39,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index d61a538..0fa7ee4 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); memory_params->DdrFreqLimit = 1600; } diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 2d1b363..7b29137 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index cff0096..e3edd29 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +29,7 @@ #define MEM_SINGLE_CHANC 0xc void variant_memory_init_params( - MEMORY_INIT_UPD *const params, const int spd_index) + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -58,14 +58,12 @@ if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map, - sizeof(params->DqByteMapCh0) * 2); - memcpy(params->DqsMapCpu2DramCh0, dqs_map, - sizeof(params->DqsMapCpu2DramCh0) * 2); - memcpy(params->RcompResistor, RcompResistor, - sizeof(params->RcompResistor)); - memcpy(params->RcompTarget, targeted_rcomp, - sizeof(params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 4c7fa23..e73aa3c 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EE_MEM_ID 0x3 @@ -51,12 +51,10 @@ if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, targeted_rcomp, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Gerrit-Change-Number: 32741 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32742 Change subject: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms ...................................................................... mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. In case of Kunimitsu we also can't have a better typed solution because of the FSP1.1/FSP2.0 dual port. Just replicating the functions per channel is probably the best we can do. CID=1401341, 1401344 Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/spd.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd.h M src/mainboard/intel/saddlebrook/spd/spd_util.c 7 files changed, 60 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32742/1 diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f25f88b..1a474da 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -30,8 +30,10 @@ MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index ee1ddd5..10992f0 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -26,8 +26,10 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_data1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f..e8b42ee 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,10 @@ return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index b173628..6dcc92d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -20,23 +20,33 @@ #include "boardid.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 6, 5, 4, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 2, 3, 0, 1, 6, 7, 4, 5 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db..7b2687f 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -63,8 +63,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3..47587ed 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,10 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a..7f27c31 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,23 +17,33 @@ #include <string.h> #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Gerrit-Change-Number: 32742 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Build FSB detection unconditionally
by Kyösti Mälkki (Code Review) 19 Sep '19

19 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31341 Change subject: cpu/intel/common: Build FSB detection unconditionally ...................................................................... cpu/intel/common: Build FSB detection unconditionally Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/Makefile.inc 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/31341/1 diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index b67ca85..ef6c0a4 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c + +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c +smm-y += fsb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Gerrit-Change-Number: 31341 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()
by Frans Hendriks (Code Review) 19 Sep '19

19 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33252 Change subject: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() ...................................................................... security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() To support multi digists the tlcl_extend() for TPM2 expects TPML_DIGEST_VALUE pointer as input argument. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 3 files changed, 65 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33252/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..df1ca3b 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -4,6 +4,7 @@ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Copyright 2017 Facebook Inc. * Copyright 2018 Siemens AG + * Copyright 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -209,7 +210,28 @@ if (!digest) return TPM_E_IOERROR; - result = tlcl_extend(pcr, digest, NULL); + if (CONFIG(TPM2)) { + TPML_DIGEST_VALUES tpml_digests; + + tpml_digests.count = 1; + switch (digest_algo) { + case VB2_HASH_SHA1: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA1; + memcpy(tpml_digests.digests[0].digest.sha1, digest, + sizeof(TPMU_HA)); + break; + case VB2_HASH_SHA256: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA256; + memcpy(tpml_digests.digests[0].digest.sha256, digest, + sizeof(TPMU_HA)); + break; + default: + return TPM_E_IOERROR; + } + result = tlcl_extend(pcr, (uint8_t *)&tpml_digests, NULL); + } else { + result = tlcl_extend(pcr, digest, NULL); + } if (result != TPM_SUCCESS) return result; diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..4574b4f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -126,24 +126,53 @@ } /* - * The caller will provide the digest in a 32 byte buffer, let's consider it a - * sha256 digest. + * The caller will provide the digest in a 32 byte buffer */ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest) { struct tpm2_pcr_extend_cmd pcr_ext_cmd; struct tpm2_response *response; + int i; + TPML_DIGEST_VALUES *tpml_digests; pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; - pcr_ext_cmd.digests.count = 1; - pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; - memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + tpml_digests = (TPML_DIGEST_VALUES *)in_digest; + pcr_ext_cmd.digests.count = tpml_digests->count; + + for (i = 0; i < tpml_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + tpml_digests->digests[i].hashAlg; + switch (tpml_digests->digests[i].hashAlg) { + case TPM_ALG_SHA1: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha1, + tpml_digests->digests[i].digest.sha1, + sizeof(TPMU_HA)); + break; + case TPM_ALG_SHA256: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha256, + tpml_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + } + } response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); - printk(BIOS_INFO, "%s: response is %x\n", + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if ((tpml_digests->count == 1) && + (tpml_digests->digests[0].hashAlg == TPM_ALG_ERROR) && + (tpml_digests->digests[0].digest.invalidate_pcrs == 1) && + response && (response->hdr.tpm_code & ~TPM_RC_N_MASK) == + (TPM_RC_P | TPM_RC_HASH)) { + printk(BIOS_SPEW, "%s: TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", __func__, response ? response->hdr.tpm_code : -1); if (!response || response->hdr.tpm_code) return TPM_E_IOERROR; diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..b11a9f4 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -79,6 +79,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +/* Table 15 - TPM_RC Constants (Actions) */ +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Gerrit-Change-Number: 33252 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Use common tsc_freq_mhz()
by Kyösti Mälkki (Code Review) 18 Sep '19

18 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31342 Change subject: cpu/intel/common: Use common tsc_freq_mhz() ...................................................................... cpu/intel/common: Use common tsc_freq_mhz() Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/intel/haswell/Makefile.inc D src/cpu/intel/haswell/tsc_freq.c M src/cpu/intel/model_2065x/Makefile.inc D src/cpu/intel/model_2065x/tsc_freq.c M src/cpu/intel/model_206ax/Makefile.inc D src/cpu/intel/model_206ax/tsc_freq.c 7 files changed, 12 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31342/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d06739c..f53baa0 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -13,6 +13,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> #include <console/console.h> @@ -105,3 +106,14 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +unsigned long tsc_freq_mhz(void) +{ + int ret, fsb, ratio; + + ret = get_fsb_tsc(&fsb, &ratio); + if (ret < 0) + die("TSC frequency not known\n"); + + return 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); +} diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index c317c09..87da59b 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,5 @@ ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c -romstage-y += tsc_freq.c romstage-y += ../car/romstage.c ramstage-y += acpi.c @@ -12,7 +10,6 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) ramstage-y += monotonic_timer.c diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c deleted file mode 100644 index b05cae5..0000000 --- a/src/cpu/intel/haswell/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "cpu/intel/haswell/haswell.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index ec8643a..b8e474d 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,9 +10,6 @@ subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += acpi.c diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c deleted file mode 100644 index 041785b..0000000 --- a/src/cpu/intel/model_2065x/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "model_2065x.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d193e60..6339ba0 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,9 +17,6 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_206ax/tsc_freq.c b/src/cpu/intel/model_206ax/tsc_freq.c deleted file mode 100644 index 545ca5f..0000000 --- a/src/cpu/intel/model_206ax/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "model_206ax.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Gerrit-Change-Number: 31342 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
by Bill XIE (Code Review) 17 Sep '19

17 Sep '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31631 Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ...................................................................... mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller Some T430s variants has a Thunderbolt controller wired to PCIe port #5, so it had better be left on for T430s. (T431s do not have that) The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/1 diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff30702..ee94979 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/31631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Gerrit-Change-Number: 31631 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Drop PSP Secure OS from build
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31075 Change subject: [WIP] binaryPI: Drop PSP Secure OS from build ...................................................................... [WIP] binaryPI: Drop PSP Secure OS from build For pcengines/apu2 variants we do not even send DRAM ready message to PSP. Possibly some GFX/DRM depends of running PSP but these devices are headless. And we don't support fTPM inside PSP either. Reduces blob footprint in SPI from 466 KiB to 234KiB. Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31075/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index e990f9d..81fe7ff 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,13 +85,12 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif - ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ @@ -104,12 +103,12 @@ SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Gerrit-Change-Number: 31075 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: [WIP] binaryPI: Move Hudson firmware higher in CBFS
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31074 Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ...................................................................... [WIP] binaryPI: Move Hudson firmware higher in CBFS Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31074/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 22e38c7..e990f9d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,7 +72,11 @@ # # EC ROM should be 64K aligned. +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif ifeq ($(CONFIG_HUDSON_PSP), y) @@ -191,6 +195,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/31074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Gerrit-Change-Number: 31074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: [WIP] binaryPI: Refactor Makefile for PSP directory
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31073 Change subject: [WIP] binaryPI: Refactor Makefile for PSP directory ...................................................................... [WIP] binaryPI: Refactor Makefile for PSP directory Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 15 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31073/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c7cd757..22e38c7 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -74,77 +74,39 @@ HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) -## ifeq ($(CONFIG_HUDSON_PSP), y) -## -### 0 -## ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif -## + + ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -###1 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###3 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###2 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin -endif - -###4 PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin - -###95 SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin - -###9 PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key -###12 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin -endif - -###13 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin -endif - -###18 -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -endif - endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -- To view, visit https://review.coreboot.org/c/coreboot/+/31073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Gerrit-Change-Number: 31073 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Pass reset gpio parameter to BL31
by Tristan Hsieh (Code Review) 17 Sep '19

17 Sep '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31605 Change subject: google/kukui: Pass reset gpio parameter to BL31 ...................................................................... google/kukui: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter. Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31605/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..489762d 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -14,10 +14,13 @@ */ #include <device/device.h> +#include <soc/bl31_plat_params.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/usb.h> +#include "gpio.h" + static void configure_emmc(void) { const gpio_t emmc_pin[] = { @@ -37,10 +40,28 @@ setup_usb_host(); } +static void register_reset_to_bl31(void) +{ + static struct bl31_gpio_param param_reset = { + .h = { + .type = PARAM_RESET, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_HIGH, + .direction = BL31_GPIO_DIR_OUT, + }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_param(&param_reset.h); +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Gerrit-Change-Number: 31605 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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