Change in ...coreboot[master]: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31631
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Some T430s variants has a Thunderbolt controller wired to PCIe port #5, so it had better be left on for T430s. (T431s do not have that)
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE persmule@gmail.com --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/1
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff30702..ee94979 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1"
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 1:
Currently, under Debian GNU/Linux (stable and testing), the Thunderbolt controller is identified as a PCIe switch (each port of the switch is identified as a device, and connected with an internal PCI bus). If a device is coldplugged in Thunderbolt port, the whole PCI subtree containing the Thunderbolt controller will be enumerated successfully, but if a device is hotplugged, only the PCIe port of the controller facing upstream is brought up, without everything behind it.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/31631/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31631/1//COMMIT_MSG@9 PS1, Line 9: has have
https://review.coreboot.org/#/c/31631/1//COMMIT_MSG@10 PS1, Line 10: do does
https://review.coreboot.org/#/c/31631/1//COMMIT_MSG@10 PS1, Line 10: T431s do not have : that Please add a dot/period at the end of the sentence.
Hello Alexander Couzens, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31631
to look at the new patch set (#2).
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE persmule@gmail.com --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/2
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/31631/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/31631/1//COMMIT_MSG@9 PS1, Line 9: has
have
Done
https://review.coreboot.org/c/coreboot/+/31631/1//COMMIT_MSG@10 PS1, Line 10: do
does
Done
https://review.coreboot.org/c/coreboot/+/31631/1//COMMIT_MSG@10 PS1, Line 10: T431s do not have : that
Please add a dot/period at the end of the sentence.
Done
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device
is hotplugged into it, You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it,
You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it,
You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Yes. Everything else has one detection gpio: Bluetooth, wwan, dGPU, ...
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it,
You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Yes. Everything else has one detection gpio: Bluetooth, wwan, dGPU, ...
If there is one detection gpio for the TB controller, how can I mark it? The gpio.c generated by autoport on t430s with TB controller running vendor firmware do have meaningful differences with the gpio.c in coreboot's tree.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it,
You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Yes. Everything else has one detection gpio: Bluetooth, wwan, dGPU, ...
If there is one detection gpio for the TB controller, how can I mark it? The gpio.c generated by autoport on t430s with TB controller running vendor firmware do have meaningful differences with the gpio.c in coreboot's tree.
Check schematics or compare inteltool output between devices that have a TB and one that doesn't have one. If none is possible, just mark it with a TODO.
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3:
Patch Set 3: Code-Review+1
Is there a gpio to detect the Thunderbolt controller at runtime?
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it,
You mean a gpio to detect the TB controller hidden from the pci-e bus due to absence of downstream devices?
Yes. Everything else has one detection gpio: Bluetooth, wwan, dGPU, ...
If there is one detection gpio for the TB controller, how can I mark it? The gpio.c generated by autoport on t430s with TB controller running vendor firmware do have meaningful differences with the gpio.c in coreboot's tree.
Check schematics or compare inteltool output between devices that have a TB and one that doesn't have one. If none is possible, just mark it with a TODO.
By comparing the gpio.c generated by autoport on a t430s that have a TB and the gpio.c in coreboot's tree, I fount that gpio27 is set as GPIO-INPUT on devices that have a TB, while it is set as GPIO-OUTPUT-HIGH on the gpio.c in coreboot's tree (it might reflex the config of devices that do not have a TB).
Is gpio27 the detection gpio for TB we are looking for? And if it is, what should be done to the code in the next step?
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 5:
By comparing the gpio.c generated by autoport on a t430s that have a TB and the gpio.c in coreboot's tree, I fount that gpio27 is set as GPIO-INPUT on devices that have a TB, while it is set as GPIO-OUTPUT-HIGH on the gpio.c in coreboot's tree (it might reflex the config of devices that do not have a TB).
Is gpio27 the detection gpio for TB we are looking for? And if it is, what should be done to the code in the next step?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 5: Code-Review+2
Patch Set 5:
By comparing the gpio.c generated by autoport on a t430s that have a TB and the gpio.c in coreboot's tree, I fount that gpio27 is set as GPIO-INPUT on devices that have a TB, while it is set as GPIO-OUTPUT-HIGH on the gpio.c in coreboot's tree (it might reflex the config of devices that do not have a TB).
Is gpio27 the detection gpio for TB we are looking for? And if it is, what should be done to the code in the next step?
It might be used for TB, but I would expect the GPIO to be input on all boards. It would change level if TB is installed, compared to a board where it isn't.
If you want to add a TODO that's fine for me.
Hello Alexander Couzens, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31631
to look at the new patch set (#6).
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type (Wistron LSN-4 11263-1), Boards with an additional discreet GPU, Boards with an additional TB controller (Wistron LSN-4 11271-1), each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE persmule@gmail.com --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/6
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 6:
Patch Set 5: Code-Review+2
Patch Set 5:
By comparing the gpio.c generated by autoport on a t430s that have a TB and the gpio.c in coreboot's tree, I fount that gpio27 is set as GPIO-INPUT on devices that have a TB, while it is set as GPIO-OUTPUT-HIGH on the gpio.c in coreboot's tree (it might reflex the config of devices that do not have a TB).
Is gpio27 the detection gpio for TB we are looking for? And if it is, what should be done to the code in the next step?
It might be used for TB, but I would expect the GPIO to be input on all boards. It would change level if TB is installed, compared to a board where it isn't.
If you want to add a TODO that's fine for me.
TODO added.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31631 )
Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ......................................................................
mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type (Wistron LSN-4 11263-1), Boards with an additional discreet GPU, Boards with an additional TB controller (Wistron LSN-4 11271-1), each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE persmule@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff30702..ee94979 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1"
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)