Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31074
Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ......................................................................
[WIP] binaryPI: Move Hudson firmware higher in CBFS
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB.
Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions.
NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading.
Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31074/1
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 22e38c7..e990f9d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,7 +72,11 @@ # # EC ROM should be 64K aligned.
+ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif
ifeq ($(CONFIG_HUDSON_PSP), y)
@@ -191,6 +195,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31074 )
Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ......................................................................
Patch Set 1:
Is this a bug in AvalonXhciEnvService? Could you explain a little bit this "off-by-one" error? I am willing to fix it if possible.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31074 )
Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ......................................................................
Patch Set 1:
Patch Set 1:
Is this a bug in AvalonXhciEnvService? Could you explain a little bit this "off-by-one" error? I am willing to fix it if possible.
In MullinsPI, GetRomSigPtr() while() loop returns one step early? I must have hit the error to find it out...
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31074
to look at the new patch set (#2).
Change subject: binaryPI: Move Hudson firmware higher in CBFS ......................................................................
binaryPI: Move Hudson firmware higher in CBFS
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB.
Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions.
NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading.
Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31074/2
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31074 )
Change subject: binaryPI: Move Hudson firmware higher in CBFS ......................................................................
Patch Set 2:
Patch Set 1:
Patch Set 1:
Is this a bug in AvalonXhciEnvService? Could you explain a little bit this "off-by-one" error? I am willing to fix it if possible.
In MullinsPI, GetRomSigPtr() while() loop returns one step early? I must have hit the error to find it out...
Ahh, right... I have missed it. It should be MswAddr <= 0xFFF8. Maybe at some point I will locate it in binary and patch few bits...
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31074 )
Change subject: binaryPI: Move Hudson firmware higher in CBFS ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31074 )
Change subject: binaryPI: Move Hudson firmware higher in CBFS ......................................................................
binaryPI: Move Hudson firmware higher in CBFS
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB.
Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions.
NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading.
Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index a7fcd99..cfe800d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,7 +72,11 @@ # # EC ROM should be 64K aligned.
+ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif
ifeq ($(CONFIG_HUDSON_PSP), y)
@@ -191,6 +195,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)