coreboot-gerrit June 2019

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Change in ...coreboot[master]: sb/intel/bd82x6x: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 30 Sep '19

30 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33040 Change subject: sb/intel/bd82x6x: Use common final SPI OPs setup ...................................................................... sb/intel/bd82x6x: Use common final SPI OPs setup This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/lpc.c 3 files changed, 24 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33040/1 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..1ad58b8 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -56,7 +56,14 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" - register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }" + register "spi.ops" = "{ {0x01, WRITE_NO_ADDR }, + {0x02, WRITE_WITH_ADDR }, + {0x03, READ_WITH_ADDR }, + {0x05, READ_NO_ADDR }, + {0x20, WRITE_WITH_ADDR }, + {0x9f, READ_NO_ADDR }, + {0xad, WRITE_NO_ADDR }, + {0x04, WRITE_NO_ADDR } }" device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 29f6881..d04cbec 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <southbridge/intel/common/spi.h> #include <stdint.h> struct southbridge_intel_bd82x6x_config { @@ -97,14 +98,7 @@ uint32_t spi_uvscc; uint32_t spi_lvscc; - struct { - uint8_t opprefixes[2]; - struct { - uint8_t needs_address; - uint8_t is_write; - uint8_t op; - } ops[8]; - } spi; + struct intel_spi_config spi; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7737501..9615698 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -38,6 +38,7 @@ #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -875,34 +876,6 @@ static void lpc_final(struct device *dev) { - u16 spi_opprefix = SPI_OPPREFIX; - u16 spi_optype = SPI_OPTYPE; - u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }; - - /* Configure SPI opcode menu; devicetree may override defaults. */ - const config_t *const config = dev->chip_info; - if (config && config->spi.ops[0].op) { - unsigned int i; - - spi_opprefix = 0; - spi_optype = 0; - spi_opmenu[0] = 0; - spi_opmenu[1] = 0; - for (i = 0; i < sizeof(spi_opprefix); ++i) - spi_opprefix |= config->spi.opprefixes[i] << i * 8; - for (i = 0; i < sizeof(spi_opmenu); ++i) { - spi_optype |= - config->spi.ops[i].is_write << 2 * i | - config->spi.ops[i].needs_address << (2 * i + 1); - spi_opmenu[i / 4] |= - config->spi.ops[i].op << (i % 4) * 8; - } - } - RCBA16(0x3894) = spi_opprefix; - RCBA16(0x3896) = spi_optype; - RCBA32(0x3898) = spi_opmenu[0]; - RCBA32(0x389c) = spi_opmenu[1]; - /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || @@ -918,6 +891,19 @@ } } +void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + /* Devicetree may override defaults. */ + const config_t *const config = dev->chip_info; + + if (config) + return; + + if (config->spi.ops[0].op != 0) + memcpy(spi_config, &config->spi, sizeof(config->spi)); +} + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Gerrit-Change-Number: 33040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asrock/h110m: rewrite gpio config using macros
by Maxim Polyakov (Code Review) 28 Sep '19

28 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33565 Change subject: mb/asrock/h110m: rewrite gpio config using macros ...................................................................... mb/asrock/h110m: rewrite gpio config using macros Use macros from the intel/common/block/include/intelblocks/gpio_defs.h instead of the raw values of the DW0/1 registers to determine the GPIO ports configuration for this board. The pch-pads-parser(1) utility was used to create this configuration from inteltool logs. [1] https://github.com/maxpoliak/pch-pads-parser Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/include/gpio.h 1 file changed, 228 insertions(+), 240 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33565/1 diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae9911..4063087 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -19,254 +19,242 @@ #include <soc/gpe.h> #include <soc/gpio.h> -#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ - _PAD_CFG_STRUCT(val, config0, config1) - /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC1 */ + PAD_CFG_GPI(GPP_A11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A12, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */ + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* SUS_ACK# */ + PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPI(GPP_B0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B1, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), /* CPU_GP3 */ + PAD_CFG_GPI(GPP_B5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B6, NONE, PLTRST), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_B8, 5K_PU, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B10, NONE, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x04000000, 0x00000000), /* GPIO */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), /* SPKR */ + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO */ + PAD_CFG_GPI(GPP_B18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B22, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), /* PCHHOT# */ + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPI(GPP_C5, NONE, PLTRST), /* GPIO */ /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), /* UART0_TXD */ + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), /* UART0_RTS# */ + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), /* UART0_CTS# */ + PAD_CFG_GPI(GPP_C12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C19, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), /* UART2_TXD */ + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* UART2_RTS# */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), /* GPIO */ + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI(GPP_D0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D1, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D4, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), /* I2S_SFRM */ + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), /* I2S_TXD */ + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* I2S_RXD */ + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* I2S_SCLK */ + PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D18, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), /* DMIC_DATA0 */ + PAD_CFG_GPI(GPP_D21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), /* SATAXPCIE0 */ + PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), /* SATAXPCIE1 */ + PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), /* SATAXPCIE2 */ + PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* CPU_GP0 */ + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* SATA_DEVSLP2 */ + PAD_CFG_GPI(GPP_E7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_OC3# */ + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI(GPP_F0, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */ + PAD_NC(GPP_F2, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F4, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F7, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC4# */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* USB_OC5# */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* USB_OC6# */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI(GPP_G0, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G1, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G2, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G3, NONE, PWROK), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* GPIO */ + PAD_CFG_GPI(GPP_G5, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G6, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G7, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G13, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G15, 0, PLTRST), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* SMI# */ + PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, PLTRST), /* GPIO */ + PAD_NC(GPP_H1, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_H2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H4, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H23, NONE, PWROK), /* GPIO */ + /* -------- GPIO Group GPD -------- */ + PAD_CFG_GPI(GPD0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_GPI(GPD6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPD7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ + PAD_CFG_GPI(GPP_I4, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ + PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), /* DDPD_CTRLDATA */ }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ + + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC1 */ + + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */ + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* SUS_ACK# */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529 Gerrit-Change-Number: 33565 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 18

Change in ...coreboot[master]: mb/lenovo/x131e: enable mSATA slot
by James (Code Review) 28 Sep '19

28 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31364 Change subject: mb/lenovo/x131e: enable mSATA slot ...................................................................... mb/lenovo/x131e: enable mSATA slot Per google/stout. Functionality untested. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 --- M src/mainboard/lenovo/x131e/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31364/1 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 628c4eb..d20abdf 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -49,8 +49,8 @@ register "gpi6_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports - register "sata_port_map" = "0x1" + # Enable SATA ports 0 (2.5 inch) and 1 (mSATA) + register "sata_port_map" = "0x3" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" -- To view, visit https://review.coreboot.org/c/coreboot/+/31364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Gerrit-Change-Number: 31364 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/lenovo/x131e: correct USB port config
by James (Code Review) 28 Sep '19

28 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31365 Change subject: mb/lenovo/x131e: correct USB port config ...................................................................... mb/lenovo/x131e: correct USB port config Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc --- M src/mainboard/lenovo/x131e/romstage.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31365/1 diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..7e326e7 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -38,20 +38,20 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, - {1, 1, 0}, - {0, 1, 1}, - {1, 1, 1}, - {1, 0, 2}, - {1, 0, 2}, - {0, 0, 3}, - {0, 0, 3}, - {0, 1, 4}, - {1, 1, 4}, - {0, 0, 5}, - {0, 0, 5}, - {0, 0, 6}, - {1, 0, 6}, + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 0, -1}, /* P13: Bluetooth (no OC) */ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/c/coreboot/+/31365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Gerrit-Change-Number: 31365 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX
by Frans Hendriks (Code Review) 27 Sep '19

27 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33442 Change subject: vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX ...................................................................... vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX To avoid confusion use VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT config values. Inlcude verfied_boot and mboot subdirectories as CPPFLAGS when measured boot or verified boot is enabled. This allows to generate binary with measured boot enabled only. BUG=N/A TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/Makefile.inc 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33442/1 diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index 26b324b..16f17fd 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,6 +1,6 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Eltan B.V. +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -16,12 +16,9 @@ subdirs-y += verified_boot subdirs-y += mboot -ifeq ($(CONFIG_MBOOT), y) +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/mboot CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/include -endif - -ifeq ($(CONFIG_VERIFIED_BOOT), y) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/verified_boot endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a Gerrit-Change-Number: 33442 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: src/mainboard: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 26 Sep '19

26 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33684 Change subject: src/mainboard: Use 'include <stdlib.h>' when appropriate ...................................................................... src/mainboard: Use 'include <stdlib.h>' when appropriate Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/gardenia/gpio.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/esd/atom15/gpio.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/intel/bayleybay_fsp/gpio.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/minnowmax/gpio.c M src/mainboard/intel/strago/gpio.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c M src/mainboard/roda/rk886ex/m3885.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/siemens/mc_tcu3/gpio.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/mainboard/ti/beaglebone/leds.c 20 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33684/1 diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 7c5f47b..2013fa5 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -14,8 +14,8 @@ */ #include <soc/southbridge.h> -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> #include "gpio.h" diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..66c49ad 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <commonlib/endian.h> +#include <stdlib.h> #include "fw_cfg.h" #include "fw_cfg_if.h" diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c index b9c7829..248e6d8 100644 --- a/src/mainboard/esd/atom15/gpio.c +++ b/src/mainboard/esd/atom15/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 9db26c7..9916df4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -16,7 +16,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <stdlib.h> +#include <stddef.h> #include <boardid.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..feb8c02 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853..6d180fd 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b357..4049b2d 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 9a6b64e..14298d4 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -14,9 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> +#include <stddef.h> #include <string.h> - #include <boardid.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c index 27b22c5..0ac1f9b 100644 --- a/src/mainboard/intel/bayleybay_fsp/gpio.c +++ b/src/mainboard/intel/bayleybay_fsp/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4c93051..801dbc8 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -19,9 +19,9 @@ #include <console/console.h> #include <device/device.h> #include <gpio.h> -#include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> + #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index b0f78c8..08b89d1 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ed9ae4b..0fe55d2 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -16,8 +16,8 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <stdlib.h> #include <boardid.h> + #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index 757d8da..9924ec0 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -11,16 +11,15 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <delay.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ - #include <Porting.h> #include <AGESA.h> #include <northbridge/amd/agesa/dimmSpd.h> + #include "sema.h" /* Write data block to slave on SMBUS0. */ diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c index 78d1ad6..32edaf5 100644 --- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c index c9d5426..e280e7c 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" #define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K) diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 60a4f48..4b97dfc 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -15,12 +15,11 @@ */ #include <types.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <delay.h> - #include <ec/acpi/ec.h> + #include "m3885.h" #define TH0LOW 80 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 237d551..3530ff4 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -14,8 +14,8 @@ * */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <arch/early_variables.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 23c6f96..d6d7106 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 8ac6ff1..3d43181 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include <string.h> #include <console/console.h> #include <soc/otp.h> diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index a4889b9..97b544a 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -13,8 +13,8 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <cpu/ti/am335x/gpio.h> -#include <stdlib.h> #include "leds.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Gerrit-Change-Number: 33684 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 5

Change in ...coreboot[master]: mb,sb: Use get_acpi_table_revision()
by HAOUAS Elyes (Code Review) 26 Sep '19

26 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33437 Change subject: mb,sb: Use get_acpi_table_revision() ...................................................................... mb,sb: Use get_acpi_table_revision() Change-Id: Icce0e8c01732ec0d5797554c0c35606686c2b0e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/torpedo/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/nvidia/mcp55/fadt.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33437/1 diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 3400fcb..9d11378 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -50,7 +50,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 7669761..afe72c0 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 6aaa702..d72ad63 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/33437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icce0e8c01732ec0d5797554c0c35606686c2b0e7 Gerrit-Change-Number: 33437 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: soc/fsp_broadwell_de: fix flashconsole support for platform
by Matt DeVillier (Code Review) 25 Sep '19

25 Sep '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32880 Change subject: soc/fsp_broadwell_de: fix flashconsole support for platform ...................................................................... soc/fsp_broadwell_de: fix flashconsole support for platform CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert to using own spi implementation, and use CAR_GLOBAL as in early versions of CB:21107 Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/Makefile.inc A src/soc/intel/fsp_broadwell_de/spi.c 3 files changed, 607 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32880/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..85e7249 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,12 +12,11 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SOUTHBRIDGE_INTEL_COMMON - select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET select PARALLEL_MP select SMP select IOAPIC + select SPI_FLASH select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 0a23170..4b2a24d 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -12,6 +12,9 @@ subdirs-y += fsp romstage-y += gpio.c +romstage-y += spi.c + +ramstage-y += spi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += northcluster.c diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c new file mode 100644 index 0000000..7eb3b7a --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file is derived from the flashrom project. */ +#include <arch/early_variables.h> +#include <stdint.h> +#include <stdlib.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <spi_flash.h> +#include <spi-generic.h> + +typedef struct spi_slave ich_spi_slave; + +static int g_ichspi_lock CAR_GLOBAL = 0; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __packed ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned int databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller g_cntlr CAR_GLOBAL; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#define SPI_OFFSET_MASK 0x3ff + +static uint8_t readb_(const void *addr) +{ + uint8_t v = read8(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static uint16_t readw_(const void *addr) +{ + uint16_t v = read16(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static uint32_t readl_(const void *addr) +{ + uint32_t v = read32(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static void writeb_(uint8_t b, void *addr) +{ + write8(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void writew_(uint16_t b, void *addr) +{ + write16(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void writel_(uint32_t b, void *addr) +{ + write32(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr->bbar); +} + +void spi_init(void) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + uint8_t bios_cntl; + ich9_spi_regs *ich9_spi; + +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = pcidev_on_root(31, 0); +#endif + + rcba = pci_read_config32(dev, 0xf0); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->bbar = &ich9_spi->bbar; + cntlr->preop = &ich9_spi->preop; + ich_set_bbar(0); + + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint16_t optypes; + uint8_t opmenu[cntlr->menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!car_get_var(g_ichspi_lock)) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr->optype); + return 0; + } + + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr->menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr->optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", + trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(uint16_t bitmask, int wait_til_set) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + int timeout = 40000; /* This will result in 400 ms */ + uint16_t status = 0; + + while (timeout--) { + status = readw_(cntlr->status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr->status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bytesout, + din, bytesin, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bytesout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bytesin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); + + spi_setup_type(&trans); + opcode_index = spi_setup_opcode(&trans); + if (opcode_index < 0) + return -1; + with_address = spi_setup_offset(&trans); + if (with_address < 0) + return -1; + + if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr->preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr->preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bytesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr->control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + goto spi_xfer_exit; + } + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr->databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr->databytes); + else + data_length = min(trans.bytesin, cntlr->databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr->data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr->databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr->control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr->data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + +spi_xfer_exit: + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr->preop); + + return 0; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + +static const struct spi_ctrlr spi_ctrlr = { + .xfer_vector = xfer_vectors, + .max_xfer_size = member_size(ich9_spi_regs, fdata), +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/32880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Gerrit-Change-Number: 32880 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

8 22

Change in ...coreboot[master]: cpu/intel/common: Extend FSB detection to cover TSC
by Kyösti Mälkki (Code Review) 23 Sep '19

23 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31340 Change subject: cpu/intel/common: Extend FSB detection to cover TSC ...................................................................... cpu/intel/common: Extend FSB detection to cover TSC Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 23 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31340/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 83220de..d06739c 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -18,14 +18,13 @@ #include <console/console.h> #include <commonlib/helpers.h> -static int get_fsb(void) +static int get_fsb_tsc(int *fsb, int *ratio) { struct cpuinfo_x86 c; static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; msr_t msr; - int ret = -2; get_fms(&c, cpuid_eax(1)); switch (c.x86) { @@ -33,49 +32,61 @@ switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; break; case 0x25: /* Nehalem BCLK fixed at 133MHz */ - ret = 133; + *fsb = 133; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - ret = 100; + *fsb = 100; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; } break; case 0xf: /* Netburst */ msr = rdmsr(MSR_EBC_FREQUENCY_ID); + *ratio = msr.lo >> 24; switch (c.x86_model) { case 0x2: - ret = f2x_fsb[(msr.lo >> 16) & 7]; + *fsb = f2x_fsb[(msr.lo >> 16) & 7]; break; case 0x3: case 0x4: case 0x6: - ret = core2_fsb[(msr.lo >> 16) & 7]; + *fsb = core2_fsb[(msr.lo >> 16) & 7]; break; } + default: + return -2; } - return ret; + if (*fsb > 0) + return 0; + return -1; } int get_ia32_fsb(void) { - int ret; + int ret, fsb, ratio; - ret = get_fsb(); + ret = get_fsb_tsc(&fsb, &ratio); if (ret == -1) printk(BIOS_ERR, "FSB not found\n"); if (ret == -2) printk(BIOS_ERR, "CPU not supported\n"); - return ret; + if (ret < 0) + return ret; + + return fsb; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/31340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Gerrit-Change-Number: 31340 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 17

Change in ...coreboot[master]: sb/intel/common/fw: Make make aware that it needs binaries
by Nico Huber (Code Review) 20 Sep '19

20 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33327 Change subject: sb/intel/common/fw: Make make aware that it needs binaries ...................................................................... sb/intel/common/fw: Make make aware that it needs binaries Change-Id: I40c3979b84341cb88c7e9a5084c1a97230ea5503 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/common/firmware/Makefile.inc 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33327/1 diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 898ab60..eb23847 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -31,6 +31,16 @@ IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) endif +add_intel_firmware: $(CONFIG_IFD_BIN_PATH) +ifeq ($(CONFIG_HAVE_ME_BIN),y) +add_intel_firmware: $(CONFIG_ME_BIN_PATH) +endif +ifeq ($(CONFIG_HAVE_GBE_BIN),y) +add_intel_firmware: $(CONFIG_GBE_BIN_PATH) +endif +ifeq ($(CONFIG_HAVE_EC_BIN),y) +add_intel_firmware: $(CONFIG_EC_BIN_PATH) +endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/33327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c3979b84341cb88c7e9a5084c1a97230ea5503 Gerrit-Change-Number: 33327 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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