coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/soc/amd/picasso: Update UARTs
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33767 Change subject: src/soc/amd/picasso: Update UARTs ...................................................................... src/soc/amd/picasso: Update UARTs Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/uart.c 2 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33767/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index b9d1ab5..b06e101 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -59,8 +59,11 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_UART_MAX_PORT 3 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d5d3006..339bd27 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -16,12 +16,19 @@ #include <console/uart.h> #include <soc/southbridge.h> +static const uintptr_t uart_addresses[] = { + APU_UART0_BASE, + APU_UART1_BASE, + APU_UART2_BASE, + APU_UART3_BASE, +}; + uintptr_t uart_platform_base(int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx < 0 || idx > APU_UART_MAX_PORT) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_addresses[uart]; } unsigned int uart_platform_refclk(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Gerrit-Change-Number: 33767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Update all PSP and amdfw.rom building
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33764 Change subject: soc/amd/picasso: Update all PSP and amdfw.rom building ...................................................................... soc/amd/picasso: Update all PSP and amdfw.rom building Add Kconfig options and Makefile comand line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are NDA only. See PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 385 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33764/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5fefbde..5f0bb22 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,43 +75,6 @@ int default 200 -config ROMSTAGE_ADDR - hex "DRAM address of first execution stage" - default 0x9b00000 - help - The base address where romstage should be linked and the PSP - uncompresses the image. - -config ROMSTAGE_MAX_SIZE - hex "Size of first execution stage" - default 0x10000 - help - The base address where romstage should be linked. This is the - uncompressed size of romstage. - -config DCACHE_RAM_BASE - hex - default 0x9fa0000 - help - Although this product begins execution in DRAM, the DCACHE symbols - are maintained for backward compatibility with the romstage - mechanism for migrating values from CAR. Notice that in this - design, stack writes modify memory and are not contained solely - within the cache. As a result, this memory must be marked reserved - and not usable by the OS. - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK - hex - default 0x4000 - help - The amount of stack space allocated prior to placing the stack - in cbmem. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -155,7 +118,7 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" config PICASSO_SATA_MODE int "SATA Mode" @@ -263,14 +226,65 @@ ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. -config USE_PSPSECUREOS - bool "Include PSP SecureOS blobs in AMD firmware" - default y - help - Include the PspSecureOs, PspTrustlet and TrustletKey binaries - in the amdfw section. +config DIMM_SPD_SIZE + int + default 512 # DDR4 - If unsure, answer 'y' +config RO_REGION_ONLY + string + depends on CHROMEOS + default "apu/amdfw" + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + +menu "PSP Configuration Options" + +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 + help + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config DCACHE_RAM_BASE + hex + default 0x9f70000 + help + Although this product begins execution in DRAM, the DCACHE symbols + are maintained for backward compatibility with the romstage + mechanism for migrating values from CAR. Notice that in this + design, stack writes modify memory and are not contained solely + within the cache. As a result, this memory must be marked reserved + and not usable by the OS. + +config DCACHE_RAM_SIZE + hex + default 0x40000 + +config DCACHE_BSP_STACK_SIZE + depends on C_ENVIRONMENT_BOOTBLOCK + hex + default 0x4000 + help + The amount of stack space allocated prior to placing the stack + in cbmem. config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" @@ -313,25 +327,95 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config DIMM_SPD_SIZE - int - default 512 # DDR4 +config AMD_PUBKEY_FILE + string "AMD public Key" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" -config RO_REGION_ONLY - string - depends on CHROMEOS - default "apu/amdfw" - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config MAINBOARD_POWER_RESTORE - def_bool n +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 help - This option determines what state to go to once power is restored - after having been lost in S0. Select this option to automatically - return to S0. Otherwise the system will remain in S5 once power - is restored. + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config PSP_APCB_FILE + string "APCB file" + help + The name of the AGESA Parameter Customization Block. + +config PSP_APOB_DESTINATION + hex + default 0x9f00000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_NV_ADDRESS + hex "Base address of APOB NV" + default 0xffa68000 + help + Location in flash where the PSP can find the S3 restore information. + Place this on a boundary that the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache base address should be used. + +config PSP_APOB_NV_SIZE + hex "Size of APOB NV to be reserved" + default 0x10000 + help + Size of the S3 restore information. Make this a multiple of the + size the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache size should be used. + +config USE_PSPSCUREOS + bool "Include PSP SecureOS blobs in PSP build" + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool "Include MP2 blobs in PSP build" + default y + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_S0I3_FW + bool "Include S0I3 blob in PSP build" + help + Select this item to include the S0i3 file into the PSP build. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + number? this feature requires a signed whitelist image and + bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_BL_FILE + string "Whitelist-capable bootloader file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/PspBootLoader_WL_RV.sbin" + +config PSP_WHITELIST_FILE + string "Debug whitelist file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/whitelist.bin" + +endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 43ae48b..cac6ab5 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,6 +1,6 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. +# Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc. # 2013 - 2014 Sage Electronic Engineering, LLC # All rights reserved. # @@ -113,93 +113,230 @@ # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) -### 0 +# +# PSP Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=ST -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +# type = 0x1 +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x5 +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSignedRV.key -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x3 +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_RV.sbin -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +# types = 0x8 and 0x18 +PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +# type = 0x9 +PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin + +# type = 0xb +PSP_SOFTFUSE="0x0000000010000001" + +ifeq ($(CONFIG_USE_PSPSCUREOS),y) +# types = 0x2, 0xc +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin +# type = 0x13 +PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +# type = 0x21 +PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin +# type = 0x24 +PSP_SECG1_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) - -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +# type = 0x25 +PSP_MP2FW1_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin +# BIOS type = 0x6a +PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +else +PSP_SOFTFUSE="0x0000000030000001" endif -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +# type = 0x28 +PSP_DRIVERS_FILE=$(top)/$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +PSP_S0I3_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin endif +# types = 0x30 - 0x37 +PSP_ABL0_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +PSPBTLDR_FILE=$(CONFIG_PSP_WHITELIST_BL_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) +PSP_BIOSBIN_SIZE=$(CONFIG_ROMSTAGE_MAX_SIZE) + +# type = 0x63 +PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) +PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) + +# type2 = 0x64, 0x65 +PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin + +# type = 0x66 +PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +xOPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +OOPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) +OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) +OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) +OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) +OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) +OPT_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) +OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) +OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) +OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) +OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) +OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) +OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) +OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) +OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) +OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) +OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) +OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) +OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) +OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) +OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) +OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +OPT_APCB_FILE=$(call add_opt_prefix, $(PSP_APCB_FILE), --apcb) +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) +OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base) +OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size) +OPT_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) +OPT_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) +OPT_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) +OPT_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) +OPT_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) +OPT_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) +OPT_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) +OPT_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) +OPT_UCODE_FILE1=$(call add_opt_prefix, $(PSP_UCODE_FILE1), --instance 0 --ucode) +OPT_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) +OPT_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) +OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ + $(call strip_quotes, $(SMUFWM_FN_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(call strip_quotes, $(PSP_APCB_FILE)) \ + $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(call strip_quotes, $(PSP_PMUI_FILE1)) \ + $(call strip_quotes, $(PSP_PMUI_FILE2)) \ + $(call strip_quotes, $(PSP_PMUI_FILE3)) \ + $(call strip_quotes, $(PSP_PMUI_FILE4)) \ + $(call strip_quotes, $(PSP_PMUD_FILE1)) \ + $(call strip_quotes, $(PSP_PMUD_FILE2)) \ + $(call strip_quotes, $(PSP_PMUD_FILE3)) \ + $(call strip_quotes, $(PSP_PMUD_FILE4)) \ + $(call strip_quotes, $(PSP_UCODE_FILE1)) \ + $(call strip_quotes, $(PSP_UCODE_FILE2)) \ + $(call strip_quotes, $(PSP_UCODE_FILE3)) \ + $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_ABL0_FILE)) \ + $(call strip_quotes, $(PSP_ABL1_FILE)) \ + $(call strip_quotes, $(PSP_ABL2_FILE)) \ + $(call strip_quotes, $(PSP_ABL3_FILE)) \ + $(call strip_quotes, $(PSP_ABL4_FILE)) \ + $(call strip_quotes, $(PSP_ABL5_FILE)) \ + $(call strip_quotes, $(PSP_ABL6_FILE)) \ + $(call strip_quotes, $(PSP_ABL7_FILE)) \ + $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ + $(call strip_quotes, $(PSP_SECG1_FILE)) \ + $(call strip_quotes, $(PSP_SECG2_FILE)) \ + $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ + $(call_strip_quotes, $(PSP_S0I3_FILE)) \ + $(call_strip_quotes, $(PSP_IKEK_FILE)) \ + $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -210,29 +347,65 @@ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ $(OPT_SMUFIRMWARE2_FILE) \ $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_APCB_FILE) \ + $(OPT_APOB_ADDR) \ + $(OPT_APOBNV_ADDR) \ + $(OPT_APOBNV_SIZE) \ + $(OPT_BIOSBIN_FILE) \ + $(OPT_BIOSBIN_DEST) \ + $(OPT_BIOSBIN_SIZE) \ + $(OPT_SOFTFUSE) \ + $(OPT_PMUI_FILE1) \ + $(OPT_PMUI_FILE2) \ + $(OPT_PMUI_FILE3) \ + $(OPT_PMUI_FILE4) \ + $(OPT_PMUD_FILE1) \ + $(OPT_PMUD_FILE2) \ + $(OPT_PMUD_FILE3) \ + $(OPT_PMUD_FILE4) \ + $(OPT_UCODE_FILE1) \ + $(OPT_UCODE_FILE2) \ + $(OPT_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ + --token-unlock \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf +$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -259,11 +432,4 @@ endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -cbfs-files-y += smu_fw -cbfs-files-y += smu_fw2 -smu_fw-file := $(SMUFWM_FILE) -smu_fw-type := raw -smu_fw2-file := $(SMUFIRMWARE2_FILE) -smu_fw2-type := raw - endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/33764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Gerrit-Change-Number: 33764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: superio: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 20 Oct '19

20 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32830 Change subject: superio: Use 'include <stdlib.h>' when appropriate ...................................................................... superio: Use 'include <stdlib.h>' when appropriate Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/intel/i8900/superio.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8671f/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/early_serial.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/via/vt1211/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83697hf/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 60 files changed, 38 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32830/1 diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 4719923..1e833c4 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "f71805f.h" static void f71805f_init(struct device *dev) diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c index 200b21e..05132cc 100644 --- a/src/superio/fintek/f71808a/superio.c +++ b/src/superio/fintek/f71808a/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include "f71808a.h" diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index da998d0..2cd1bb1 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include "f71859.h" static void f71859_init(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 634888b..a044dc2 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f71863fg.h" static void f71863fg_init(struct device *dev) diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 15fdf3e..67b39ef 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include "fintek_internal.h" diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 3316ee2..7694f41 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f71872.h" static void f71872_init(struct device *dev) diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index e55ec57..106ab0e 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -19,7 +19,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <console/console.h> -#include <stdlib.h> #include "chip.h" #include "f81216h.h" diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index b6156ee..d62fc82 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f81865f.h" static void f81865f_init(struct device *dev) diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index 53a5aac..c66bf27 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -19,8 +19,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f81866d.h" #include "fintek_internal.h" diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c index 24805bc..e56c192 100644 --- a/src/superio/intel/i8900/superio.c +++ b/src/superio/intel/i8900/superio.c @@ -14,13 +14,13 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/device.h> #include <device/pnp.h> #include <drivers/uart/uart8250reg.h> -#include "i8900.h" #include <arch/io.h> +#include "i8900.h" + static void pnp_enter_ext_func_mode(struct device *dev) { outb(0x80, dev->path.pnp.port); diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1b93036..7f60f22 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -17,10 +17,10 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> +#include <stddef.h> #include "env_ctrl.h" #include "env_ctrl_chip.h" diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c index 1ed8fe0..d7169e6 100644 --- a/src/superio/ite/it8528e/superio.c +++ b/src/superio/ite/it8528e/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8528e.h" diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index 5fdfcef..0448832 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 70da2ab..761c9fb 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> + #include "it8671f.h" static void init(struct device *dev) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 6f096b0..2004236 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8712f.h" diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index de1ef0d..a3b8ec4 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8716f.h" diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index ed15955..297aead 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/ite/common/env_ctrl.h> #include <superio/conf_mode.h> diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index cf3ca3f..5426992 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -18,8 +18,8 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> + #include "it8721f.h" static void init(struct device *dev) diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 7107bb4..58a837e 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -18,7 +18,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/ite/common/env_ctrl.h> #include "chip.h" diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index ed46e73..7c21f10 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -20,7 +20,6 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <delay.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "chip.h" /* FIXME */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 4f8f967..1c4b476 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87309.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 33f27e1..f8ad4d5 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87360.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 6d8c66e..3cf62cd 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87366.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..c90ebd9 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87382.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index cef7ff7..87dd265 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87384.h" static struct device_operations ops = { diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..4a5bed2 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87392.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f867ff3..f98ba84 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87417.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 42f5434..397c3ea 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -16,8 +16,8 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "pc97317.h" static void init(struct device *dev) diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200..493e0ce 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -16,7 +16,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "nct5104d.h" #include "chip.h" diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index e8249d4..3084687 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> #include <arch/acpi.h> #include <superio/conf_mode.h> diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index e399c0a..78e07b6 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6776.h" diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 49e6306..7ef3488 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6779d.h" diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 3a6d740..23d5a6f 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6791d.h" diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index c1f557e..f11e75a 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <option.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index c666818..aeb394a 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "wpcm450.h" static void init(struct device *dev) diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 522d647..857caa1 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -17,7 +17,6 @@ #include <device/pnp.h> #include <console/console.h> #include <device/smbus.h> -#include <stdlib.h> #include <pc80/keyboard.h> void m3885_configure_multikey(void); diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 0bfd3b8..5a62478 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -21,7 +21,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "dme1737.h" static void dme1737_init(struct device *dev) diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index 0ee9850..3706dec 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -17,7 +17,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include "fdc37n972.h" diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index e43e791..3c2ded5 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "kbc1100.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 6ac2d6d..bfe7b45 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -24,7 +24,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47b272.h" /** diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ad8153f..a18714d 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47b397.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index cd13854..7b88c72 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -23,7 +23,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47m10x.h" /** diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 80ed456..4aeeb23 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47m15x.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index b8e5c0b..9bda334 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -16,7 +16,7 @@ #include <arch/io.h> #include <device/pnp.h> #include <stdint.h> -#include <stdlib.h> + #include "lpc47n207.h" /* diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index b10e8a1..246a853 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -25,7 +25,7 @@ #include <console/console.h> #include <device/smbus.h> #include <assert.h> -#include <stdlib.h> + #include "lpc47n217.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 610f685..c21cdda 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <device/smbus.h> #include <assert.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 74b8b2e..12e9af2 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "mec1308.h" static void mec1308_init(struct device *dev) diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 5e49aa7..0e102e6 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -19,7 +19,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include "sch4037.h" diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index a192831..6ed6954 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include "sio1036.h" diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c index b8243ec..cf432a0 100644 --- a/src/superio/smsc/sio10n268/superio.c +++ b/src/superio/smsc/sio10n268/superio.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> + #include "sio10n268.h" static void init(struct device *dev) diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 4ce006d..aa5af38 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -35,7 +35,6 @@ #include <superio/conf_mode.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <stdlib.h> /* The following Super I/O chips are currently supported by this driver: */ #define LPC47M172 0x14 diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c index 4d7c8de..24443c2 100644 --- a/src/superio/via/vt1211/superio.c +++ b/src/superio/via/vt1211/superio.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "vt1211.h" static u8 hwm_io_regs[] = { diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 9e15037..bd9900b 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -17,7 +17,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "w83627dhg.h" static void w83627dhg_enable_UR2(struct device *dev) diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 88fbc31..7fe6a2f 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> + #include "w83627ehg.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 318eaa4..4365652 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> + #include "w83627hf.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 82974ba..e783740 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -18,8 +18,8 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <stdint.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "w83627uhg.h" /* diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 0735f04..4a995d6 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> #include <arch/acpi.h> #include <superio/conf_mode.h> diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index a3c132c..4323088 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <console/console.h> #include <lib.h> -#include <stdlib.h> + #include "chip.h" #include "w83697hf.h" diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index b4f316b..b11e5be 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -20,7 +20,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "w83977tf.h" static void w83977tf_init(struct device *dev) diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index ae4fce4..70457e6 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <drivers/uart/uart8250reg.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "chip.h" #include "wpcd376i.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Gerrit-Change-Number: 32830 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: mediatek/mt8183: modify vdram1 voltage
by hsin-hsiung wang (Code Review) 18 Oct '19

18 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33186 Change subject: mediatek/mt8183: modify vdram1 voltage ...................................................................... mediatek/mt8183: modify vdram1 voltage Dram DVFS needs calibration with different vdram1 voltage to get correct parameters, so we provide a api to change vdram1 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram1 voltage with multimeter Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33186/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 02937ba..c90e6e4 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -26,6 +26,9 @@ PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, }; @@ -38,5 +41,7 @@ void mt6358_init(void); void pmic_set_power_hold(bool enable); +unsigned int pmic_get_vdram1_vol(void); +void pmic_set_vdram1_vol(unsigned int vdram_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7054243..ea4e7bd 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -733,6 +733,29 @@ pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); } +unsigned int pmic_get_vdram1_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return (500000 + vol_reg * 12500); +} + +void pmic_set_vdram1_vol(unsigned int vdram_uv) +{ + unsigned int vol_reg; + + if (500000 > vdram_uv) + vol_reg = 0; + else if (vdram_uv > 1300000) + vol_reg = 0x40; + else + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Gerrit-Change-Number: 33186 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

6 27

Change in ...coreboot[master]: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
by Arthur Heymans (Code Review) 16 Oct '19

16 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33549 Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges ...................................................................... [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges Most mainboards do nothing but setting up a similar decode range so move it to a common place. All IO ports below 0x1000 are allocated to the LPC device by default so this should not be an issue. Lynxpoint does this too. TODO remove most mainboard specific setups. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0082c91..ef3ee77 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,8 +258,16 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -static void pch_enable_lpc_gen_decode(void) +static void pch_enable_lpc_decode(void) { + /* Set COM1/COM2 decode range */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN + | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; @@ -279,9 +287,10 @@ void early_pch_init(void) { - pch_enable_lpc(); - pch_enable_lpc_gen_decode(); + pch_enable_lpc_decode(); + + pch_enable_lpc(); pch_enable_bars(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Gerrit-Change-Number: 33549 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 17

Change in ...coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
by Michał Żygowski (Code Review) 14 Oct '19

14 Oct '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753 Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI ...................................................................... src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 --- M src/soc/intel/fsp_baytrail/smm.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1 diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 84f8d28..149272d 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <string.h> +#include <bootstate.h> #include <soc/iomap.h> #include <soc/pmc.h> @@ -124,3 +125,16 @@ "d" (APM_CNT) ); } + +static void finalize_chipset(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + /* Lock sleep stretching policy and set SMI lock. */ + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), + read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) + | SLPSX_STR_POL_LOCK | SMI_LOCK); + outb(APM_CNT_FINALIZE, APM_CNT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/30753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 Gerrit-Change-Number: 30753 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/skylake: Use common cpu/intel/car romstage entry
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33019 Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry ...................................................................... soc/intel/skylake: Use common cpu/intel/car romstage entry Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/romstage/Makefile.inc M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33019/1 diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e929eba..7bb9d4b 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d6..7eebc3a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -17,6 +17,7 @@ #include <arch/early_variables.h> #include <arch/symbols.h> #include <assert.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -135,25 +136,27 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(unsigned long bist) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); +} + +void platform_enter_postcar(void) +{ + uintptr_t top_of_ram; + struct postcar_frame pcf; + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Gerrit-Change-Number: 33019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33058 Change subject: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM ...................................................................... [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM Fetching the option table from cbfs each time is slowing things down and adds a vulnerability during S3 resume. Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/pc80/rtc/mc146818rtc.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33058/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 535ba33..5ef8506 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -25,6 +25,7 @@ #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 #define CBMEM_ID_CBTABLE_FWD 0x43425443 +#define CBMEM_ID_CMOS_TABLE 0x366f1abb #define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 @@ -88,6 +89,7 @@ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ { CBMEM_ID_CBTABLE_FWD, "COREBOOTFWD" }, \ + { CBMEM_ID_CMOS_TABLE, "CMOS " }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ { CBMEM_ID_COVERAGE, "COVERAGE " }, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3667354..ee16cf1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <bcd.h> +#include <cbmem.h> #include <fallback.h> #include <stdint.h> #include <version.h> @@ -272,6 +273,15 @@ static enum cb_err get_layout(struct cmos_option_table *ct) { +#if !(defined(__PRE_RAM__) || ENV_SMM) + struct cmos_option_table *table; + table = cbmem_find(CBMEM_ID_CMOS_TABLE); + if (table) { + ct = table; + return CB_SUCCESS; + } +#endif + LOCK_NVRAM_CBFS_SPINLOCK(); if (locate_cmos_layout(&rdev) != CB_SUCCESS) { @@ -286,6 +296,14 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } +#if !(defined(__PRE_RAM__) || ENV_SMM) + table = cbmem_add(CBMEM_ID_CMOS_TABLE, region_device_sz(&rdev)); + if (table) { + memcpy(table, ct, region_device_sz(&rdev)); + ct = table; + } +#endif + return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Gerrit-Change-Number: 33058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: drivers/pc80/rtc: Move fetching and cleaning up the layout
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33057 Change subject: drivers/pc80/rtc: Move fetching and cleaning up the layout ...................................................................... drivers/pc80/rtc: Move fetching and cleaning up the layout Both get_option and set_option need to fetch the layout and clean up afterwards. Do this in a common location. Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 39 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33057/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6e37cd2..3667354 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -268,22 +268,12 @@ return CB_SUCCESS; } -enum cb_err get_option(void *dest, const char *name) +struct region_device rdev; + +static enum cb_err get_layout(struct cmos_option_table *ct) { - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - LOCK_NVRAM_CBFS_SPINLOCK(); - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; @@ -296,6 +286,32 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } + return CB_SUCCESS; +} + +static void clean_up_layout(struct cmos_option_table *ct) +{ + rdev_munmap(&rdev, ct); + UNLOCK_NVRAM_CBFS_SPINLOCK(); +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct = NULL;; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + if (!CONFIG(USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + LOCK_NVRAM_CBFS_SPINLOCK(); + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (get_layout(ct) != CB_SUCCESS) + return CB_CMOS_LAYOUT_NOT_FOUND; /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -308,23 +324,19 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_SUCCESS; } @@ -383,8 +395,7 @@ enum cb_err set_option(const char *name, void *value) { - struct cmos_option_table *ct; - struct region_device rdev; + struct cmos_option_table *ct = NULL; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -396,18 +407,8 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); + if (get_layout(ct) != CB_SUCCESS) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -420,7 +421,7 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -430,17 +431,17 @@ /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } } if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Gerrit-Change-Number: 33057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969 Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point ...................................................................... soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point This moves some boilerplate like setting up timestamps and entering postcar to a common location. Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c 2 files changed, 4 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1 diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463..8f009bd 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cc3bcd9..2a530b4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> @@ -49,8 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void platform_enter_postcar(void); - static void program_base_addresses(void) { uint32_t reg; @@ -166,18 +165,12 @@ } /* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +void mainboard_romstage_entry(unsigned long bist) { struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - program_base_addresses(); tco_disable(); @@ -215,25 +208,13 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; -- To view, visit https://review.coreboot.org/c/coreboot/+/32969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Gerrit-Change-Number: 32969 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019