Change in ...coreboot[master]: soc/intel/skylake: Use common cpu/intel/car romstage entry

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33019

Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry
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soc/intel/skylake: Use common cpu/intel/car romstage entry

Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/skylake/romstage/Makefile.inc
M src/soc/intel/skylake/romstage/romstage_fsp20.c
2 files changed, 10 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33019/1

diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index e929eba..7bb9d4b 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,4 +1,4 @@
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 96937d6..7eebc3a 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -17,6 +17,7 @@
 #include <arch/early_variables.h>
 #include <arch/symbols.h>
 #include <assert.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
@@ -135,25 +136,27 @@
    printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }

-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(unsigned long bist)
 {
    bool s3wake;
-	struct postcar_frame pcf;
-	uintptr_t top_of_ram;
    struct chipset_power_state *ps;

-	console_init();
-
    /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
    systemagent_early_init();

ps = pmc_get_power_state();
-	timestamp_add_now(TS_START_ROMSTAGE);
    s3wake = pmc_fill_power_state(ps) == ACPI_S3;
    fsp_memory_init(s3wake);
    pmc_set_disb();
    if (!s3wake)
    	save_dimm_info();
+}
+
+void platform_enter_postcar(void)
+{
+	uintptr_t top_of_ram;
+	struct postcar_frame pcf;
+
    if (postcar_frame_init(&pcf, 1*KiB))
    	die("Unable to initialize postcar frame.\n");

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33019 )

Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry
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Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/skylake: Use common cpu/intel/car romstage entry

[Arthur Heymans (Code Review)]

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33019 )

Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry
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Abandoned