coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703 Change subject: device/hypertransport: Fix regression on dev_find_slot() removal ...................................................................... device/hypertransport: Fix regression on dev_find_slot() removal The regression is with the implementation of the functions introduced in commit ad7674e device: Introduce pcidev_on_root() and friends For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are being manipulated during HyperTransport enumeration. This workaround reverts to old method of using dev_find_slot() while keeping track of whether the new method would give equivalent result. Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/device/device.c M src/device/device_const.c M src/device/hypertransport.c M src/include/device/device.h M src/include/device/pci.h 6 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1 diff --git a/Makefile.inc b/Makefile.inc index 2741b19..24b5164 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,7 +577,10 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) + +ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y) smm-y+=$(DEVICETREE_STATIC_C) +endif ####################################################################### # Clean up rules diff --git a/src/device/device.c b/src/device/device.c index 7836af1..20a4077 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,4 +1253,7 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); + + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..480ac76 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -173,6 +173,43 @@ return child; } +/*** + * Work around the devicetree topology being manipulated on-the-fly + * on systems with HyperTransport Support. + */ + +static int ht_tree_needs_fixing, ht_tree_fixup_failed; + +void ht_report_devtree_sanity(void) +{ + printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", + ht_tree_needs_fixing, ht_tree_fixup_failed); +} + +static const struct bus *ht_bus_reloc(const struct bus *parent, + pci_devfn_t devfn) +{ + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct bus *bus; + + /* HyperTransport enumeration fixes up the whacky + * topology present in static devicetree. + */ + if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status())) + return parent; + + if (devfn >= PCI_DEVFN(0x18, 0)) + return parent; + + /* One of the links is bus for devices 0:00.x to 0:17.x. */ + dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0)); + for (bus = dev->link_list; bus; bus = bus->next) + if (bus->children) + return bus; + + return NULL; +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -185,12 +222,34 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { + DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - return pcidev_path_behind(pci_domain->link_list, devfn); + + dev = pcidev_path_behind(pci_domain->link_list, devfn); + + /* Static devicetree with HyperTransport has whacky topology. */ + if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + return dev; + + DEVTREE_CONST struct device *dev_fixup, *dev_old_method; + + const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); + dev_fixup = pcidev_path_behind(root, devfn); + dev_old_method = dev_find_slot(0, devfn); + + if (ENV_RAMSTAGE) { + if (dev != dev_old_method) + ht_tree_needs_fixing++; + + if (dev_fixup != dev_old_method) + ht_tree_fixup_failed++; + } + + return dev_old_method; } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ed6b2dd..fd4961e 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -244,6 +244,13 @@ } } +static int ht_scan_chain_process = SCAN_NOT_STARTED; + +int ht_scanning_status(void) +{ + return ht_scan_chain_process; +} + static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unitid_base, @@ -276,6 +283,9 @@ /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_IN_PROGRESS; + /* See which static device nodes I have. */ old_devices = bus->children; bus->children = 0; @@ -472,6 +482,9 @@ last_func->sibling = old_devices; } + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_COMPLETE; + return next_unitid; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..40a0f58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,6 +227,7 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..41ad281 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -122,6 +122,13 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +enum { + SCAN_NOT_STARTED = 0, + SCAN_IN_PROGRESS, + SCAN_COMPLETE +}; +int ht_scanning_status(void); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/30703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Gerrit-Change-Number: 30703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: ec/google/chromeec: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 14 Nov '19

14 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32142 Change subject: ec/google/chromeec: Remove redundant use of ACPI offset operator ...................................................................... ec/google/chromeec: Remove redundant use of ACPI offset operator Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32142/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 962988e..b6c2231 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -41,7 +41,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte @@ -54,7 +53,6 @@ TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number // DFUD must be 0 for the other 31 values to be valid - Offset (0x0a), DFUD, 1, // Device Features Undefined FLSH, 1, // Flash commands present PFAN, 1, // PWM Fan control present @@ -88,7 +86,6 @@ RWSG, 1, // EC has RWSIG task enabled DEVE, 1, // EC supports device events // make sure we're within our space envelope - Offset (0x0e), Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 982ec5b..77b4708 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -17,7 +17,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */ -Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Gerrit-Change-Number: 32142 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33175 Change subject: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK VERY WIP and UNTESTED Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc 15 files changed, 42 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33175/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index dbb8982..34b74b5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -24,10 +24,6 @@ select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_206ax/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..f0c263b 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -11,6 +11,11 @@ subdirs-y += ../microcode subdirs-y += ../turbo +bootblock-y += ../../x86/early_reset.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += bootblock.c + ramstage-y += acpi.c ramstage-y += common.c @@ -31,7 +36,6 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..197e94c 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -15,13 +15,11 @@ #include <stdint.h> #include <arch/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> +#include <cpu/intel/car/bootblock.h> -#include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ @@ -32,35 +30,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -111,10 +80,8 @@ halt(); } -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..961aa7f 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c +romstage-y += early_init.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 97% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c index a5b0c81..4e416bd 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -27,8 +27,9 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <bootblock_common.h> -void pch_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -105,10 +106,6 @@ { } -void mainboard_config_superio(void) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index d5901da..ef87335 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_ACPI select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -68,16 +69,19 @@ int default 512 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 help The MRC blob requires it to be at 0xf0000000. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466..7e9c351 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,8 @@ ramstage-y += acpi.c +bootblock-y += bootblock.c + romstage-y += ram_calc.c ramstage-y += common.c diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..b4de3a4 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,11 +12,12 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> /* Just re-define this instead of including sandybridge.h. It blows up romcc. */ #define PCIEXBAR 0x60 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088..114cd6f 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -54,11 +54,11 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ - early_pch_init(); + /* Init GPIO, ... */ + romstage_pch_init(); /* Initialize superio */ - mainboard_config_superio(); +// mainboard_config_superio(); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..8b9f580 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -54,10 +54,6 @@ int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/bd82x6x/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b6023b0..7af3cec 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,12 +38,16 @@ romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c +bootblock-y += early_pch.c romstage-y += early_pch.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +bootblock-y += early_usb.c romstage-y += early_thermal.c early_me.c early_usb.c else romstage-y += early_me_mrc.c early_usb_mrc.c endif +bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0086fe3..1566faa 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> #include "pch.h" @@ -66,7 +67,7 @@ RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); enable_port80_on_lpc(); @@ -74,4 +75,6 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + bootblock_pch_init(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..0aa78ae 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,13 +258,15 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -void early_pch_init(void) +void bootblock_pch_init(void) { - pch_enable_lpc(); - pch_enable_bars(); pch_generic_setup(); +} +void romstage_pch_init(void) +{ setup_pch_gpios(&mainboard_gpio_map); } + diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 4369b5c..9d9570b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,7 +75,8 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -void early_pch_init(void); +void bootblock_pch_init(void); +void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f..6a5e636 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +bootblock-y += pmbase.c verstage-y += pmbase.c romstage-y += pmbase.c ramstage-y += pmbase.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Gerrit-Change-Number: 33175 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: northbridge/intel/sandybridge: Set up console on bootblock
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33187 Change subject: northbridge/intel/sandybridge: Set up console on bootblock ...................................................................... northbridge/intel/sandybridge: Set up console on bootblock The assmption is made that setting up southbridge gpio's is not needed for console in the bootblock. Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/Makefile.inc R src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/asrock/b75pro3-m/Makefile.inc R src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asus/h61m-cs/Makefile.inc R src/mainboard/asus/h61m-cs/early_init.c M src/mainboard/asus/maximus_iv_gene-z/Makefile.inc R src/mainboard/asus/maximus_iv_gene-z/early_init.c M src/mainboard/asus/p8h61-m_lx/Makefile.inc R src/mainboard/asus/p8h61-m_lx/early_init.c M src/mainboard/asus/p8h61-m_pro/Makefile.inc R src/mainboard/asus/p8h61-m_pro/early_init.c M src/mainboard/compulab/intense_pc/Makefile.inc R src/mainboard/compulab/intense_pc/early_init.c M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc R src/mainboard/gigabyte/ga-b75m-d3h/early_init.c M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc R src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c M src/mainboard/google/butterfly/Makefile.inc R src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/Makefile.inc R src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/Makefile.inc R src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/Makefile.inc R src/mainboard/google/stout/early_init.c M src/mainboard/hp/2570p/Makefile.inc R src/mainboard/hp/2570p/early_init.c M src/mainboard/hp/2760p/Makefile.inc R src/mainboard/hp/2760p/early_init.c M src/mainboard/hp/8460p/Makefile.inc R src/mainboard/hp/8460p/early_init.c M src/mainboard/hp/8470p/Makefile.inc R src/mainboard/hp/8470p/early_init.c M src/mainboard/hp/8770w/Makefile.inc R src/mainboard/hp/8770w/early_init.c M src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc R src/mainboard/hp/compaq_8200_elite_sff/early_init.c M src/mainboard/hp/folio_9470m/Makefile.inc R src/mainboard/hp/folio_9470m/early_init.c M src/mainboard/hp/revolve_810_g1/Makefile.inc R src/mainboard/hp/revolve_810_g1/early_init.c M src/mainboard/intel/dcp847ske/Makefile.inc R src/mainboard/intel/dcp847ske/early_init.c M src/mainboard/intel/emeraldlake2/Makefile.inc R src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/Makefile.inc R src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/l520/Makefile.inc R src/mainboard/lenovo/l520/early_init.c M src/mainboard/lenovo/s230u/Makefile.inc R src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t420/Makefile.inc R src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/Makefile.inc R src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/Makefile.inc R src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/t430s/Makefile.inc R src/mainboard/lenovo/t430s/early_init.c M src/mainboard/lenovo/t520/Makefile.inc R src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/t530/Makefile.inc R src/mainboard/lenovo/t530/early_init.c M src/mainboard/lenovo/x131e/Makefile.inc R src/mainboard/lenovo/x131e/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc R src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/early_init.c M src/mainboard/msi/ms7707/Makefile.inc R src/mainboard/msi/ms7707/early_init.c M src/mainboard/roda/rv11/Makefile.inc R src/mainboard/roda/rv11/early_init.c M src/mainboard/samsung/lumpy/Makefile.inc R src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/Makefile.inc R src/mainboard/samsung/stumpy/early_init.c M src/mainboard/sapphire/pureplatinumh61/Makefile.inc R src/mainboard/sapphire/pureplatinumh61/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 86 files changed, 135 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33187/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index a41ee25..b80d5da 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -6,3 +6,6 @@ spd.bin-type := spd ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/early_init.c similarity index 100% rename from src/mainboard/apple/macbookair4_2/romstage.c rename to src/mainboard/apple/macbookair4_2/early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 017967b..3ca89fb 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/early_init.c similarity index 100% rename from src/mainboard/asrock/b75pro3-m/romstage.c rename to src/mainboard/asrock/b75pro3-m/early_init.c diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/early_init.c similarity index 100% rename from src/mainboard/asus/h61m-cs/romstage.c rename to src/mainboard/asus/h61m-cs/early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index f81e828..dd91210 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c similarity index 100% rename from src/mainboard/asus/maximus_iv_gene-z/romstage.c rename to src/mainboard/asus/maximus_iv_gene-z/early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 7c1bf9e..0ef22db 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_lx/romstage.c rename to src/mainboard/asus/p8h61-m_lx/early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_pro/romstage.c rename to src/mainboard/asus/p8h61-m_pro/early_init.c diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/early_init.c similarity index 100% rename from src/mainboard/compulab/intense_pc/romstage.c rename to src/mainboard/compulab/intense_pc/early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 07fc277..53aae3d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -20,3 +20,6 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c rename to src/mainboard/gigabyte/ga-b75m-d3h/early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c rename to src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 8033e1c..9c6920e 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -22,3 +22,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/early_init.c similarity index 100% rename from src/mainboard/google/butterfly/romstage.c rename to src/mainboard/google/butterfly/early_init.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 89bb365..84e6e5e 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -41,3 +41,6 @@ spd.bin-file := $(SPD_BIN) spd.bin-type := spd romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/early_init.c similarity index 100% rename from src/mainboard/google/link/romstage.c rename to src/mainboard/google/link/early_init.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 393d582..9f057e5 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -20,3 +20,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/early_init.c similarity index 100% rename from src/mainboard/google/parrot/romstage.c rename to src/mainboard/google/parrot/early_init.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index be1f0fe..652dc6f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -25,3 +25,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/early_init.c similarity index 100% rename from src/mainboard/google/stout/romstage.c rename to src/mainboard/google/stout/early_init.c diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2570p/Makefile.inc +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/early_init.c similarity index 100% rename from src/mainboard/hp/2570p/romstage.c rename to src/mainboard/hp/2570p/early_init.c diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2760p/Makefile.inc +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/early_init.c similarity index 100% rename from src/mainboard/hp/2760p/romstage.c rename to src/mainboard/hp/2760p/early_init.c diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/early_init.c similarity index 100% rename from src/mainboard/hp/8460p/romstage.c rename to src/mainboard/hp/8460p/early_init.c diff --git a/src/mainboard/hp/8470p/Makefile.inc b/src/mainboard/hp/8470p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8470p/Makefile.inc +++ b/src/mainboard/hp/8470p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/early_init.c similarity index 100% rename from src/mainboard/hp/8470p/romstage.c rename to src/mainboard/hp/8470p/early_init.c diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc index d57c9b5..b480ae4 100644 --- a/src/mainboard/hp/8770w/Makefile.inc +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -14,3 +14,6 @@ ## romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/early_init.c similarity index 100% rename from src/mainboard/hp/8770w/romstage.c rename to src/mainboard/hp/8770w/early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c similarity index 100% rename from src/mainboard/hp/compaq_8200_elite_sff/romstage.c rename to src/mainboard/hp/compaq_8200_elite_sff/early_init.c diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ b/src/mainboard/hp/folio_9470m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/early_init.c similarity index 100% rename from src/mainboard/hp/folio_9470m/romstage.c rename to src/mainboard/hp/folio_9470m/early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc index 7a211f4..e5c8647 100644 --- a/src/mainboard/hp/revolve_810_g1/Makefile.inc +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -19,3 +19,6 @@ # FIXME: Other varients with same size onboard ram may exist. SPD_SOURCES = hynix_4g + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/early_init.c similarity index 100% rename from src/mainboard/hp/revolve_810_g1/romstage.c rename to src/mainboard/hp/revolve_810_g1/early_init.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 4d516f6..3803149 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -2,3 +2,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/early_init.c similarity index 100% rename from src/mainboard/intel/dcp847ske/romstage.c rename to src/mainboard/intel/dcp847ske/early_init.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index b3bf53f..f2d7b97 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c similarity index 100% rename from src/mainboard/intel/emeraldlake2/romstage.c rename to src/mainboard/intel/emeraldlake2/early_init.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/early_init.c similarity index 100% rename from src/mainboard/kontron/ktqm77/romstage.c rename to src/mainboard/kontron/ktqm77/early_init.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2aa7f0f..f1a1016 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -18,3 +18,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/early_init.c similarity index 100% rename from src/mainboard/lenovo/l520/romstage.c rename to src/mainboard/lenovo/l520/early_init.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index dea2e4e..0e4c5e8 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -15,3 +15,6 @@ SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/early_init.c similarity index 100% rename from src/mainboard/lenovo/s230u/romstage.c rename to src/mainboard/lenovo/s230u/early_init.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420/romstage.c rename to src/mainboard/lenovo/t420/early_init.c diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420s/romstage.c rename to src/mainboard/lenovo/t420s/early_init.c diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index ada25f7..0ca0ecd 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -3,3 +3,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430/romstage.c rename to src/mainboard/lenovo/t430/early_init.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d70c22e..05763f9 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -19,3 +19,6 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430s/romstage.c rename to src/mainboard/lenovo/t430s/early_init.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/early_init.c similarity index 100% rename from src/mainboard/lenovo/t520/romstage.c rename to src/mainboard/lenovo/t520/early_init.c diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/early_init.c similarity index 100% rename from src/mainboard/lenovo/t530/romstage.c rename to src/mainboard/lenovo/t530/early_init.c diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/early_init.c similarity index 100% rename from src/mainboard/lenovo/x131e/romstage.c rename to src/mainboard/lenovo/x131e/early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index ee08d78..5a83f28 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -19,3 +19,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/romstage.c rename to src/mainboard/lenovo/x1_carbon_gen1/early_init.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..c988b80 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 100% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/early_init.c similarity index 100% rename from src/mainboard/lenovo/x230/romstage.c rename to src/mainboard/lenovo/x230/early_init.c diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 3dae61e..ea30f64 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1 +1,4 @@ romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/early_init.c similarity index 100% rename from src/mainboard/msi/ms7707/romstage.c rename to src/mainboard/msi/ms7707/early_init.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 5b5ca65..fd4c498 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -19,3 +19,6 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/early_init.c similarity index 100% rename from src/mainboard/roda/rv11/romstage.c rename to src/mainboard/roda/rv11/early_init.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 7f8f966..21c855f 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -30,3 +30,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/lumpy/romstage.c rename to src/mainboard/samsung/lumpy/early_init.c diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index a91a061..f50c637 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/stumpy/romstage.c rename to src/mainboard/samsung/stumpy/early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 7c555f9..a584a16 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c similarity index 100% rename from src/mainboard/sapphire/pureplatinumh61/romstage.c rename to src/mainboard/sapphire/pureplatinumh61/early_init.c diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 336b47e..3f7bae2 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/common/gpio.h> #include <elog.h> static void early_pch_reset_pmcon(void) @@ -53,11 +54,8 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO ... */ - romstage_pch_init(); - - /* Initialize superio */ - mainboard_config_superio(); + /* Init GPIO */ + setup_pch_gpios(&mainboard_gpio_map); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index ef64825..452fb4f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,7 +14,9 @@ */ #include <cpu/intel/car/bootblock.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <device/pci_ops.h> +#include <bootblock_common.h> #include "pch.h" /* @@ -78,3 +80,10 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); } + +void bootblock_mainboard_early_init(void) +{ + pch_enable_lpc(); + + mainboard_config_superio(); +} diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index c166f79..5619133 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -264,10 +264,3 @@ pch_generic_setup(); } - -void romstage_pch_init(void) -{ - pch_enable_lpc(); - - setup_pch_gpios(&mainboard_gpio_map); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9d9570b..9102bb5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); void bootblock_pch_init(void); -void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Gerrit-Change-Number: 33187 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 5

Change in ...coreboot[master]: soc/intel/broadwell: Use common INTEL_SB SPI code
by Arthur Heymans (Code Review) 10 Nov '19

10 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33203 Change subject: soc/intel/broadwell: Use common INTEL_SB SPI code ...................................................................... soc/intel/broadwell: Use common INTEL_SB SPI code Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/spi.c 3 files changed, 1 insertion(+), 670 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33203/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index deb5ef3..4698a3b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,6 +23,7 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index a79fa46..148ed58 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -63,11 +63,6 @@ ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c -bootblock-y += spi.c -romstage-y += spi.c -postcar-y += spi.c -ramstage-y += spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c romstage-y += stage_cache.c postcar-y += stage_cache.c diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c deleted file mode 100644 index 01d2830..0000000 --- a/src/soc/intel/broadwell/spi.c +++ /dev/null @@ -1,665 +0,0 @@ -/* - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include <stdint.h> -#include <stdlib.h> -#include <bootstate.h> -#include <commonlib/helpers.h> -#include <delay.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/spi.h> - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -void spi_init(void) -{ - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - ich9_spi_regs *ich9_spi; - - rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); - - /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } - - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", - trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 6000; /* This will result in 60 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, - "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI" - " chip driver use CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - /* http://www.intel.com/content/dam/www/public/us/en/documents/ - * datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815- - * n2806-j1850-j1750-datasheet.pdf - */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -/* Use first empty Protected Range Register to cover region of flash */ -static int spi_flash_protect(const struct spi_flash *flash, - const struct region *region, - const enum ctrlr_prot_type type) -{ - u32 start = region_offset(region); - u32 end = start + region_sz(region) - 1; - u32 reg; - u32 protect_mask = 0; - int prr; - - /* Find first empty PRR */ - for (prr = 0; prr < SPI_PRR_MAX; prr++) { - reg = SPIBAR32(SPI_PRR(prr)); - if (reg == 0) - break; - } - if (prr >= SPI_PRR_MAX) { - printk(BIOS_ERR, "ERROR: No SPI PRR free!\n"); - return -1; - } - - /* Set protected range base and limit */ - reg = ((end >> SPI_PRR_SHIFT) & SPI_PRR_MASK); - reg <<= SPI_PRR_LIMIT_SHIFT; - reg |= ((start >> SPI_PRR_SHIFT) & SPI_PRR_MASK); - - switch (type) { - case WRITE_PROTECT: - protect_mask |= SPI_PRR_WPE; - break; - case READ_PROTECT: - protect_mask |= SPI_PRR_RPE; - break; - case READ_WRITE_PROTECT: - protect_mask |= (SPI_PRR_RPE | SPI_PRR_WPE); - break; - default: - printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); - return -1; - } - - reg |= protect_mask; - - /* Set the PRR register and verify it is protected */ - SPIBAR32(SPI_PRR(prr)) = reg; - reg = SPIBAR32(SPI_PRR(prr)); - if (!(reg & protect_mask)) { - printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr); - return -1; - } - - printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n", - __func__, prr, start, end); - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), - .flash_protect = spi_flash_protect, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/33203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d Gerrit-Change-Number: 33203 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: soc/intel/broadwell: Use common SB RTC code
by Arthur Heymans (Code Review) 10 Nov '19

10 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33202 Change subject: soc/intel/broadwell: Use common SB RTC code ...................................................................... soc/intel/broadwell: Use common SB RTC code Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pmutil.c 2 files changed, 1 insertion(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33202/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 89a3c4c..deb5ef3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -22,6 +22,7 @@ select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 322e96f..00db615 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -451,32 +451,6 @@ return sci_irq; } -int rtc_failure(void) -{ - u8 reg8; - int rtc_failed; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - } - - return !!rtc_failed; -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} - int vboot_platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/33202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Gerrit-Change-Number: 33202 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: sb/intel/common: Make linking rtc.c conditional
by Arthur Heymans (Code Review) 10 Nov '19

10 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33201 Change subject: sb/intel/common: Make linking rtc.c conditional ...................................................................... sb/intel/common: Make linking rtc.c conditional Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 13 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33201/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d81ab8a..89a3c4c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,6 +20,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..f8c54ca 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -15,6 +15,7 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select PARALLEL_MP select SMP select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..c0d93c9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,6 +30,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 42717b0..6189f2f 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,10 @@ bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_RTC + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n depends on SOUTHBRIDGE_INTEL_COMMON diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ac2fd8e..c3523c9 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -66,6 +66,6 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -$(eval $(call add_to_all_stages,y,rtc.c)) +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC),rtc.c)) endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 4526cb3..8b9a786 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_RTC config EHCI_BAR hex diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 6552099..1d984a2 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,6 +2,7 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC bool config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 12640b3..cb2bb7a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,7 @@ select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d6e938..a6f8d90 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -31,6 +31,7 @@ select INTEL_HAS_TOP_SWAP select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_RTC if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 5edb8a1..3e53b9d 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b423eca..bf35a6a 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -21,6 +21,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 85c8979..60da867 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 67e20be..2540d8a 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -27,6 +27,7 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/33201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Gerrit-Change-Number: 33201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in ...coreboot[master]: [WIP]mb/asus/p5ql-em: Add mainboard
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31323 Change subject: [WIP]mb/asus/p5ql-em: Add mainboard ...................................................................... [WIP]mb/asus/p5ql-em: Add mainboard Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 1067MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure macaddress in Kconfig) - PEG slot Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI TODO: - BSEL superio pins Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p5ql-em/Kconfig A src/mainboard/asus/p5ql-em/Kconfig.name A src/mainboard/asus/p5ql-em/Makefile.inc A src/mainboard/asus/p5ql-em/acpi/ec.asl A src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl A src/mainboard/asus/p5ql-em/acpi/platform.asl A src/mainboard/asus/p5ql-em/acpi/superio.asl A src/mainboard/asus/p5ql-em/acpi_tables.c A src/mainboard/asus/p5ql-em/board_info.txt A src/mainboard/asus/p5ql-em/cmos.default A src/mainboard/asus/p5ql-em/cmos.layout A src/mainboard/asus/p5ql-em/cstates.c A src/mainboard/asus/p5ql-em/data.vbt A src/mainboard/asus/p5ql-em/devicetree.cb A src/mainboard/asus/p5ql-em/dsdt.asl A src/mainboard/asus/p5ql-em/gma-mainboard.ads A src/mainboard/asus/p5ql-em/gpio.c A src/mainboard/asus/p5ql-em/hda_verb.c A src/mainboard/asus/p5ql-em/romstage.c 19 files changed, 811 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31323/1 diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig new file mode 100644 index 0000000..07af627 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QL_EM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "asus/p5ql-em" + +config MAINBOARD_PART_NUMBER + string + default "P5QL EM" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name new file mode 100644 index 0000000..92ead65 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QL_EM + bool "P5QL EM" diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc new file mode 100644 index 0000000..6b3d94a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -0,0 +1,17 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-y += cstates.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..861561a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5ql-em/acpi/platform.asl b/src/mainboard/asus/p5ql-em/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl new file mode 100644 index 0000000..8f414f5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c new file mode 100644 index 0000000..d609a0e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt new file mode 100644 index 0000000..42d4812 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QC/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default new file mode 100644 index 0000000..ad822d5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout new file mode 100644 index 0000000..09ba5c5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -0,0 +1,104 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#436 548 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 0000000..aa7214d --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801jx/i82801jx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt new file mode 100644 index 0000000..5dd1803 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/data.vbt Binary files differ diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb new file mode 100644 index 0000000..e13d59b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -0,0 +1,169 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on # Host Bridge + subsystemid 0x1043 0x8336 + end + device pci 1.0 on # PEG + subsystemid 0x1043 0x8336 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1043 0x8336 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1043 0x8336 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1b.0 on # Audio + subsystemid 0x1043 0x82fe + end + device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on # PCIe 4 1394 controller + device pci 0.0 on + subsystemid 0x1043 0x8313 + end + end + device pci 1c.4 on # PCIe 5 Marvell IDE + device pci 0.0 on + subsystemid 0x1043 0x82a2 + end + end + device pci 1c.5 on # PCIe 6 Realtek LAN + device pci 0.0 on + subsystemid 0x1043 0x82c6 + end + end + device pci 1d.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x82d4 + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + # global + irq 0x2c = 0x92 + #floppy + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + drq 0x74 = 0x02 + end + device pnp 2e.1 on # Parallel port + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 + irq 0xf1 = 0x0c + end + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x06 + irq 0xf5 = 0x06 + end + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xdf + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1043 0x82d4 + end + device pci 1f.3 on # SMbus + subsystemid 0x1043 0x82d4 + end + device pci 1f.4 off end + device pci 1f.5 on # IDE + subsystemid 0x1043 0x82d4 + end + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl new file mode 100644 index 0000000..d7ce26e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads new file mode 100644 index 0000000..43a7d89 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c new file mode 100644 index 0000000..7bc8b9b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c new file mode 100644 index 0000000..9e54df6 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c new file mode 100644 index 0000000..da822ac --- /dev/null +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <northbridge/intel/x4x/iomap.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + /* HW EC */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); + /* TODO: FSB BSEL pins... */ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + sdram_initialize(boot_path, spd_addrmap); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Gerrit-Change-Number: 31323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 40

Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019