coreboot-gerrit June 2019

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Change in ...coreboot[master]: {cpu,device,drivers}: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33527 Change subject: {cpu,device,drivers}: Remove unused include <device/pci_ops.h> ...................................................................... {cpu,device,drivers}: Remove unused include <device/pci_ops.h> Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/pi/amd_late_init.c M src/cpu/intel/fsp_model_406dx/bootblock.c M src/device/azalia_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/intel/gma/intel_ddi.c 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33527/1 diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 8c0da9d..e105892 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -17,7 +17,6 @@ #include <bootstate.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 14cfad9..c43124a 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -20,7 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include "model_406dx.h" diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index a2849b7..9727eb6 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/azalia_device.h> #include <device/mmio.h> #include <delay.h> diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 21af5c7..59659b8 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <pc80/vga.h> #include "../common/aspeed_coreboot.h" diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 471a5d2..b475b5e 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -30,7 +30,6 @@ #include <stdlib.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/interrupt.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Gerrit-Change-Number: 33527 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33729 Change subject: src/mainboard: Remove not used #include <elog.h> ...................................................................... src/mainboard: Remove not used #include <elog.h> Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c 12 files changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33729/1 diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index e786ef5..d2f923a 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -21,7 +21,6 @@ #include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <elog.h> #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index a4a1cca..8e4cada 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -18,7 +18,6 @@ #include <baseboard/variant.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <ec/google/chromeec/smm.h> #include <gpio.h> #include <soc/iomap.h> diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 9475361..8e8c9d4 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -19,7 +19,6 @@ #include <cpu/x86/smm.h> #include <soc/pm.h> #include <soc/smm.h> -#include <elog.h> #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 807cec3..3e9f9fa 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <device/device.h> -#include <elog.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/addressmap.h> diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index c8bb813..9c4e943 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <elog.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 97d0576..7f8abab 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <elog.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index fde2bd0..3397a50 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -22,8 +22,6 @@ #include <device/device.h> #include <drivers/parade/ps8640/ps8640.h> #include <edid.h> - -#include <elog.h> #include <gpio.h> #include <soc/da9212.h> #include <soc/ddp.h> diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 5243dc9..8aa20aa 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/i2c_simple.h> #include <edid.h> -#include <elog.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 9024b6c..2de720c 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/i2c_simple.h> #include <edid.h> -#include <elog.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 6259955..52ecbf6 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/i2c_simple.h> #include <edid.h> -#include <elog.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index ba8458b..ba68df2 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index df02601..e65b153 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> #include <soc/nvs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86 Gerrit-Change-Number: 33729 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/{northbridge,soc}: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33732 Change subject: src/{northbridge,soc}: Remove not used #include <elog.h> ...................................................................... src/{northbridge,soc}: Remove not used #include <elog.h> Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/early_init.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/skylake/romstage/romstage.c 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33732/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6fef0da..606c9c7 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -20,7 +20,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <elog.h> + #include "haswell.h" static bool peg_hidden[3]; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 4d748b2..6fb4cf6 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -24,7 +24,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <elog.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> #include <soc/iomap.h> diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 854bd76..bb1bbf8 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -21,7 +21,6 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <spi-generic.h> -#include <elog.h> #include <soc/lpc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 29c4774..e0467bb 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b Gerrit-Change-Number: 33732 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/vendorcode: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33731 Change subject: src/vendorcode: Remove not used #include <elog.h> ...................................................................... src/vendorcode: Remove not used #include <elog.h> Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/google/chromeos/gnvs.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33731/1 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 44162c8..8115455 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -19,7 +19,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <elog.h> #include <fmap.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76 Gerrit-Change-Number: 33731 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: southbridge: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33730 Change subject: southbridge: Remove not used #include <elog.h> ...................................................................... southbridge: Remove not used #include <elog.h> Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33730/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 374a9d9..ccfe52d 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 16ae3c6..f7f08c8 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -19,7 +19,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index ba5e04b..b477a53 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -28,7 +28,6 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/cpu.h> -#include <elog.h> #include <string.h> #include <cbmem.h> #include <arch/acpigen.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 208075b..ac45c15 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb Gerrit-Change-Number: 33730 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Update calculation for TSC frequency
by Marshall Dawson (Code Review) 10 Sep '19

10 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33765 Change subject: soc/amd/picasso: Update calculation for TSC frequency ...................................................................... soc/amd/picasso: Update calculation for TSC frequency Remove the Family 15h step of finding the number of boost states and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff --- M src/soc/amd/picasso/tsc_freq.c 1 file changed, 3 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33765/1 diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 29121b9..2277b33 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -19,26 +19,16 @@ #include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> #include <console/console.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> unsigned long tsc_freq_mhz(void) { msr_t msr; uint8_t cpufid; uint8_t cpudid; - uint8_t boost_states; + uint8_t high_state; - /* - * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for - * MSR0000_0010. The TSC increments at the P0 frequency. According - * to the "Software P-state Numbering" section, P0 is the highest - * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). - */ - boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) - >> 2) & 0x7; - - msr = rdmsr(PSTATE_0_MSR + boost_states); + high_state = rdmsr(PS_LIM_REG).lo & 0x7; + msr = rdmsr(PSTATE_0_MSR + high_state); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Gerrit-Change-Number: 33765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add ability to disable Heci1
by Bora Guvendik (Code Review) 09 Sep '19

09 Sep '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32992 Change subject: soc/intel/cannonlake: Add ability to disable Heci1 ...................................................................... soc/intel/cannonlake: Add ability to disable Heci1 Decide if HECI1 should be hidden prior to boot to OS. BUG=none TEST=Boot to OS, verify if Heci1 is disabled Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32992/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..6bea8fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,7 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + uint8_t Heci1Disabled; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd93882..7dc1dd0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -341,6 +341,7 @@ params->ScsUfsEnabled = dev->enabled; params->Heci3Enabled = config->Heci3Enabled; + params->Heci1Disabled = config->Heci1Disabled; params->Device4Enable = config->Device4Enable; /* VrConfig Settings for 5 domains diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb..365fb9f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,7 +25,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "../chip.h" - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/32992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Gerrit-Change-Number: 32992 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

6 37

Change in ...coreboot[master]: [WIP] ssdtgen for PNP devices
by Patrick Rudolph (Code Review) 08 Sep '19

08 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33033 Change subject: [WIP] ssdtgen for PNP devices ...................................................................... [WIP] ssdtgen for PNP devices Automatically create ACPI code for PNP devices. TODO: Add HID to devicetree. Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/superio/common/chip.h A src/superio/common/ssdt.c A src/superio/common/ssdt.h 3 files changed, 386 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33033/1 diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h new file mode 100644 index 0000000..2d75c0f --- /dev/null +++ b/src/superio/common/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_CHIP_H__ +#define __SUPERIO_COMMON_CHIP_H__ + +struct common_superio_ldn_config { + const char *acpi_name; + const char *dos_device_name; + const char *acpi_hid; +}; + +#endif /* __SUPERIO_COMMON_CHIP_H__ */ diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c new file mode 100644 index 0000000..0e2c59f --- /dev/null +++ b/src/superio/common/ssdt.c @@ -0,0 +1,334 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <superio/common/chip.h> +#include <superio/common/ssdt.h> + +#include <device/device.h> +#include <device/pnp.h> +#include <arch/acpigen.h> +#include <device/pnp_def.h> +#include <console/console.h> + +#define NUM_IO 4 +#define NUM_IRQ 2 + +struct superio_dev { + const char *acpi_hid; + u16 io_base[NUM_IO]; + u8 irq[NUM_IRQ]; +}; + +static const struct superio_dev superio_devs[] = { + {"PNP0700", {0x3f0, 0x3f2, 0x3f7}, {6, }}, + {"PNP0303", {60, 64, }, {1, }}, + {"PNP0F03", {60, 64, }, {12, }}, + {"PNP0501", {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3}}, + {"PNP0400", {0x378, }, {7, }}, +}; + +static const u8 io_idx[NUM_IO] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, + PNP_IDX_IO3}; +static const u8 irq_idx[NUM_IRQ] = {PNP_IDX_IRQ0, PNP_IDX_IRQ1}; + + +static void superio_base_fill_ssdt_generator(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + acpigen_write_name_string("_HID", "PNP0C02"); + acpigen_write_name_string("_DDN", dev_name(dev)); + + /* OperationRegion("IOID", SYSTEMIO, port, 2) */ + struct opregion opreg = OPREGION("IOID", SYSTEMIO, + dev->path.pnp.port, 2); + acpigen_write_opregion(&opreg); + + struct fieldlist l[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("INDX", 8), + FIELDLIST_NAMESTR("DATA", 8), + }; + + /* Field (IOID, AnyAcc, NoLock, Preserve) + * { + * Offset (0), + * INDX, 8, + * DATA, 8, + * } */ + acpigen_write_field(opreg.name, l, ARRAY_SIZE(l), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + struct fieldlist i[] = { + FIELDLIST_OFFSET(0x07), + FIELDLIST_NAMESTR("LDN", 8), + FIELDLIST_OFFSET(0x21), + FIELDLIST_NAMESTR("SCF1", 8), + FIELDLIST_NAMESTR("SCF2", 8), + FIELDLIST_NAMESTR("SCF3", 8), + FIELDLIST_NAMESTR("SCF4", 8), + FIELDLIST_NAMESTR("SCF5", 8), + FIELDLIST_NAMESTR("SCF6", 8), + FIELDLIST_NAMESTR("SCF7", 8), + FIELDLIST_OFFSET(0x29), + FIELDLIST_NAMESTR("CKCF", 8), + FIELDLIST_OFFSET(0x2F), + FIELDLIST_NAMESTR("SCFF", 8), + FIELDLIST_NAMESTR("ACTR", 8), + FIELDLIST_OFFSET(0x60), + FIELDLIST_NAMESTR("IOAH", 8), + FIELDLIST_NAMESTR("IOAL", 8), + FIELDLIST_NAMESTR("IOH2", 8), + FIELDLIST_NAMESTR("IOL2", 8), + FIELDLIST_OFFSET(0x70), + FIELDLIST_NAMESTR("INTR", 4), + FIELDLIST_NAMESTR("INTT", 4), + FIELDLIST_OFFSET (0x74), + FIELDLIST_NAMESTR("DMCH", 8), + FIELDLIST_OFFSET(0xE0), + FIELDLIST_NAMESTR("RGE0", 8), + FIELDLIST_NAMESTR("RGE1", 8), + FIELDLIST_NAMESTR("RGE2", 8), + FIELDLIST_NAMESTR("RGE3", 8), + FIELDLIST_NAMESTR("RGE4", 8), + FIELDLIST_NAMESTR("RGE5", 8), + FIELDLIST_NAMESTR("RGE6", 8), + FIELDLIST_NAMESTR("RGE7", 8), + FIELDLIST_NAMESTR("RGE8", 8), + FIELDLIST_NAMESTR("RGE9", 8), + FIELDLIST_NAMESTR("RGEA", 8), + FIELDLIST_OFFSET(0xF0), + FIELDLIST_NAMESTR("OPT0", 8), + FIELDLIST_NAMESTR("OPT1", 8), + FIELDLIST_NAMESTR("OPT2", 8), + FIELDLIST_NAMESTR("OPT3", 8), + FIELDLIST_NAMESTR("OPT4", 8), + FIELDLIST_NAMESTR("OPT5", 8), + FIELDLIST_NAMESTR("OPT6", 8), + FIELDLIST_NAMESTR("OPT7", 8), + FIELDLIST_NAMESTR("OPT8", 8), + FIELDLIST_NAMESTR("OPT9", 8), + }; + + acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *superio_guess_hid(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IO; k++) { + if (!superio_devs[j].io_base[k]) + continue; + if (superio_devs[j].io_base[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IRQ; k++) { + if (!superio_devs[j].irq[k]) + continue; + if (superio_devs[j].irq[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + return NULL; +} + +static int ldn_resource_cnt(struct device *dev) +{ + int cnt = 0; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + cnt++; + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + cnt++; + } + return cnt; +} + +/* Add IO and IRQ resources for _CRS or _PRS */ +static void ldn_gen_resources(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base, 0, sz, 1); + size -= sz; + base += sz; + } + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + acpigen_write_irq(res->base); + } +} + +/* Add resource base and size for additional SuperIO code */ +static void ldn_gen_resources_use(struct device *dev) +{ + char name[5]; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base || !res->size) + continue; + + snprintf(name, sizeof(name), "IO%XB", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->base); + + snprintf(name, sizeof(name), "IO%XS", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->size); + } +} + +static const char *ldn_acpi_name(const struct device *dev) +{ + u8 ldn = dev->path.pnp.device & 0xff; + u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + static char name[5]; + + if (!vldn) + snprintf(name, sizeof(name), "LD%02X", ldn); + else + snprintf(name, sizeof(name), "VLD%X", vldn); + + name[4] = '\0'; + + return name; +} + + +void superio_common_fill_ssdt_generator(struct device *dev) +{ + struct common_superio_ldn_config *config = dev->chip_info; + const char *scope = acpi_device_path(dev); + const char *name = ldn_acpi_name(dev); + const char *hid = NULL; + const u8 ldn = dev->path.pnp.device & 0xff; + const u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + bool has_resources; + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + if (vldn) { + printk(BIOS_DEBUG, "%s: Ignoring virtual LDN\n", dev_path(dev)); + return; + } + + if (ldn == 0) + superio_base_fill_ssdt_generator(dev); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(name); + + if (config && config->dos_device_name) + acpigen_write_name_string("_DDN", config->dos_device_name); + + acpigen_write_name_byte("_UID", 0); + acpigen_write_name_byte("LDN", ldn); + + acpigen_write_STA(dev->enabled ? 0xf : 0); + + if (!dev->enabled) { + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + return; + } + + has_resources = ldn_resource_cnt(dev); + + /* Resources - _CRS */ + if (has_resources) { + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources - _PRS */ + acpigen_write_name("_PRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources base and size for 3rd party ACPI code */ + ldn_gen_resources_use(dev); + } + + if (config && config->acpi_hid) { + hid = config->acpi_hid; + } else { + printk(BIOS_WARNING, "%s: No HID set in devicetree\n", + dev_path(dev)); + + hid = superio_guess_hid(dev); + } + + if (hid) + acpigen_write_name_string("_HID", hid); + else + acpigen_write_name_string("_HID", "PNP0C02"); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h new file mode 100644 index 0000000..4d4e4b1 --- /dev/null +++ b/src/superio/common/ssdt.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_SSDT_H__ +#define __SUPERIO_COMMON_SSDT_H__ + +#include <device/device.h> + +void superio_common_fill_ssdt_generator(struct device *dev); +const char *superio_common_acpi_name(const struct device *dev); +void superio_set_base_dev_ops(struct device *dev); + +#endif /* __SUPERIO_COMMON_SSDT_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Gerrit-Change-Number: 33033 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 50

Change in ...coreboot[master]: src/superio/aspeed/ast2400: Add Autogen ACPI Code
by Christian Walter (Code Review) 06 Sep '19

06 Sep '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33253 Change subject: src/superio/aspeed/ast2400: Add Autogen ACPI Code ...................................................................... src/superio/aspeed/ast2400: Add Autogen ACPI Code Once the Autogen ACPI Code is merged, we can use this to autogenerate the ACPI Code for the AST2400. This is WIP. Has been tested w/ AST2400. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/superio/aspeed/ast2400/Makefile.inc M src/superio/aspeed/ast2400/superio.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33253/1 diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc index a6f8b20..9a1a8f5 100644 --- a/src/superio/aspeed/ast2400/Makefile.inc +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -16,3 +16,4 @@ ## ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/ssdt.c diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index dcb14fa..c4d0c72 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <string.h> #include <pc80/keyboard.h> +#include <superio/common/ssdt.h> #include "ast2400.h" static void ast2400_init(struct device *dev) @@ -36,6 +37,13 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *aspeed_ast2400_name(const struct device *dev) +{ + return "SIO0"; +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -43,6 +51,10 @@ .enable = pnp_enable, .init = ast2400_init, .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = aspeed_ast2400_name, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Gerrit-Change-Number: 33253 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mediatek: Pass board specific message to BL31
by Tristan Hsieh (Code Review) 05 Sep '19

05 Sep '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31604 Change subject: mediatek: Pass board specific message to BL31 ...................................................................... mediatek: Pass board specific message to BL31 Sometimes we need to pass board specific messages to BL31, so that BL31 can do board specific operation based on common code. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/bl31_plat_params.c A src/soc/mediatek/common/include/soc/bl31_plat_params.h M src/soc/mediatek/mt8183/Makefile.inc 3 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31604/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c new file mode 100644 index 0000000..eb7477a --- /dev/null +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm_tf.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return plat_params; +} diff --git a/src/soc/mediatek/common/include/soc/bl31_plat_params.h b/src/soc/mediatek/common/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..399b0d5 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/bl31_plat_params.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#include <arm-trusted-firmware/plat/mediatek/common/plat_params.h> + +void register_bl31_param(struct bl31_plat_param *param); + +#endif diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 8af3d68..fc2bbe2 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ../common/bl31_plat_params.c BL31_MAKEARGS += PLAT=mt8183 CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include -- To view, visit https://review.coreboot.org/c/coreboot/+/31604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Gerrit-Change-Number: 31604 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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