coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/security/vboot: Add config option to skip display init
by Amol N Sukerkar (Code Review) 30 Jul '19

30 Jul '19

Amol N Sukerkar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33844 Change subject: src/security/vboot: Add config option to skip display init ...................................................................... src/security/vboot: Add config option to skip display init This config option, when set, will allow the platform to skip display initialization in normal (non-developer, non-recovery) mode boot for chromeos. When not set, it allows the platform to initialize the display in non-chromeos vboot mode. TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display should initialize in ramstage when platform boots. Set CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display initialization should be skipped in coreboot. Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar(a)intel.com> Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3 --- M src/security/vboot/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/33844/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 66bcc1e..f734194 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -236,6 +236,17 @@ Add a space delimited list of filenames that should only be in the RO section. +config VBOOT_MAY_SKIP_DISPLAY_INIT + bool "Skip display initialization in normal mode" + default y if CHROMEOS + default n + help + Set this option to indicate that the configuration is for CHROMEOS + and the platform will skip display initialization on a normal (non- + recovery, non-developer) boot. When not set, the platform assumes + a non-CHROMEOS configuration with vboot and allows the display to + initialize on a normal boot. + menu "GBB configuration" config GBB_HWID -- To view, visit https://review.coreboot.org/c/coreboot/+/33844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3 Gerrit-Change-Number: 33844 Gerrit-PatchSet: 1 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/external: add opensbi for risc-v
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32393 Change subject: payloads/external: add opensbi for risc-v ...................................................................... payloads/external: add opensbi for risc-v Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A payloads/external/opensbi/COPYING.BSD A payloads/external/opensbi/Makefile A payloads/external/opensbi/README.md A payloads/external/opensbi/docs/contributing.md A payloads/external/opensbi/docs/doxygen.cfg A payloads/external/opensbi/docs/firmware/fw.md A payloads/external/opensbi/docs/firmware/fw_jump.md A payloads/external/opensbi/docs/firmware/fw_payload.md A payloads/external/opensbi/docs/firmware/payload_linux.md A payloads/external/opensbi/docs/firmware/payload_uboot.md A payloads/external/opensbi/docs/library_usage.md A payloads/external/opensbi/docs/platform/platform.md A payloads/external/opensbi/docs/platform/qemu_sifive_u.md A payloads/external/opensbi/docs/platform/qemu_virt.md A payloads/external/opensbi/docs/platform/sifive_fu540.md A payloads/external/opensbi/docs/platform_guide.md A payloads/external/opensbi/firmware/external_deps.mk A payloads/external/opensbi/firmware/fw_base.S A payloads/external/opensbi/firmware/fw_base.ldS A payloads/external/opensbi/firmware/fw_jump.S A payloads/external/opensbi/firmware/fw_jump.elf.ldS A payloads/external/opensbi/firmware/fw_payload.S A payloads/external/opensbi/firmware/fw_payload.elf.ldS A payloads/external/opensbi/firmware/objects.mk A payloads/external/opensbi/firmware/payloads/objects.mk A payloads/external/opensbi/firmware/payloads/test.elf.ldS A payloads/external/opensbi/firmware/payloads/test_head.S A payloads/external/opensbi/firmware/payloads/test_main.c A payloads/external/opensbi/include/sbi/riscv_asm.h A payloads/external/opensbi/include/sbi/riscv_atomic.h A payloads/external/opensbi/include/sbi/riscv_barrier.h A payloads/external/opensbi/include/sbi/riscv_encoding.h A payloads/external/opensbi/include/sbi/riscv_fp.h A payloads/external/opensbi/include/sbi/riscv_io.h A payloads/external/opensbi/include/sbi/riscv_locks.h A payloads/external/opensbi/include/sbi/sbi_bitops.h A payloads/external/opensbi/include/sbi/sbi_bits.h A payloads/external/opensbi/include/sbi/sbi_console.h A payloads/external/opensbi/include/sbi/sbi_const.h A payloads/external/opensbi/include/sbi/sbi_ecall.h A payloads/external/opensbi/include/sbi/sbi_ecall_interface.h A payloads/external/opensbi/include/sbi/sbi_emulate_csr.h A payloads/external/opensbi/include/sbi/sbi_error.h A payloads/external/opensbi/include/sbi/sbi_hart.h A payloads/external/opensbi/include/sbi/sbi_illegal_insn.h A payloads/external/opensbi/include/sbi/sbi_init.h A payloads/external/opensbi/include/sbi/sbi_ipi.h A payloads/external/opensbi/include/sbi/sbi_misaligned_ldst.h A payloads/external/opensbi/include/sbi/sbi_platform.h A payloads/external/opensbi/include/sbi/sbi_scratch.h A payloads/external/opensbi/include/sbi/sbi_system.h A payloads/external/opensbi/include/sbi/sbi_timer.h A payloads/external/opensbi/include/sbi/sbi_trap.h A payloads/external/opensbi/include/sbi/sbi_types.h A payloads/external/opensbi/include/sbi/sbi_unpriv.h A payloads/external/opensbi/include/sbi/sbi_version.h A payloads/external/opensbi/lib/objects.mk A payloads/external/opensbi/lib/riscv_asm.c A payloads/external/opensbi/lib/riscv_atomic.c A payloads/external/opensbi/lib/riscv_hardfp.S A payloads/external/opensbi/lib/riscv_locks.c A payloads/external/opensbi/lib/sbi_console.c A payloads/external/opensbi/lib/sbi_ecall.c A payloads/external/opensbi/lib/sbi_emulate_csr.c A payloads/external/opensbi/lib/sbi_hart.c A payloads/external/opensbi/lib/sbi_illegal_insn.c A payloads/external/opensbi/lib/sbi_init.c A payloads/external/opensbi/lib/sbi_ipi.c A payloads/external/opensbi/lib/sbi_misaligned_ldst.c A payloads/external/opensbi/lib/sbi_system.c A payloads/external/opensbi/lib/sbi_timer.c A payloads/external/opensbi/lib/sbi_trap.c A payloads/external/opensbi/platform/common/include/plat/irqchip/plic.h A payloads/external/opensbi/platform/common/include/plat/serial/sifive-uart.h A payloads/external/opensbi/platform/common/include/plat/serial/uart8250.h A payloads/external/opensbi/platform/common/include/plat/string.h A payloads/external/opensbi/platform/common/include/plat/sys/clint.h A payloads/external/opensbi/platform/common/include/plat/tinyfdt.h A payloads/external/opensbi/platform/common/irqchip/objects.mk A payloads/external/opensbi/platform/common/irqchip/plic.c A payloads/external/opensbi/platform/common/libc/objects.mk A payloads/external/opensbi/platform/common/libc/string.c A payloads/external/opensbi/platform/common/libfdt/Makefile.libfdt A payloads/external/opensbi/platform/common/libfdt/TODO A payloads/external/opensbi/platform/common/libfdt/fdt.c A payloads/external/opensbi/platform/common/libfdt/fdt.h A payloads/external/opensbi/platform/common/libfdt/fdt_addresses.c A payloads/external/opensbi/platform/common/libfdt/fdt_empty_tree.c A payloads/external/opensbi/platform/common/libfdt/fdt_overlay.c A payloads/external/opensbi/platform/common/libfdt/fdt_ro.c A payloads/external/opensbi/platform/common/libfdt/fdt_rw.c A payloads/external/opensbi/platform/common/libfdt/fdt_strerror.c A payloads/external/opensbi/platform/common/libfdt/fdt_sw.c A payloads/external/opensbi/platform/common/libfdt/fdt_wip.c A payloads/external/opensbi/platform/common/libfdt/libfdt.h A payloads/external/opensbi/platform/common/libfdt/libfdt_env.h A payloads/external/opensbi/platform/common/libfdt/libfdt_internal.h A payloads/external/opensbi/platform/common/libfdt/objects.mk A payloads/external/opensbi/platform/common/libfdt/version.lds A payloads/external/opensbi/platform/common/objects.mk A payloads/external/opensbi/platform/common/serial/objects.mk A payloads/external/opensbi/platform/common/serial/sifive-uart.c A payloads/external/opensbi/platform/common/serial/uart8250.c A payloads/external/opensbi/platform/common/sys/clint.c A payloads/external/opensbi/platform/common/sys/objects.mk A payloads/external/opensbi/platform/common/tinyfdt.c A payloads/external/opensbi/platform/kendryte/k210/config.mk A payloads/external/opensbi/platform/kendryte/k210/k210.dts A payloads/external/opensbi/platform/kendryte/k210/objects.mk A payloads/external/opensbi/platform/kendryte/k210/platform.c A payloads/external/opensbi/platform/kendryte/k210/platform.h A payloads/external/opensbi/platform/kendryte/k210/sysctl.c A payloads/external/opensbi/platform/kendryte/k210/sysctl.h A payloads/external/opensbi/platform/kendryte/k210/uarths.c A payloads/external/opensbi/platform/kendryte/k210/uarths.h A payloads/external/opensbi/platform/qemu/sifive_u/config.mk A payloads/external/opensbi/platform/qemu/sifive_u/objects.mk A payloads/external/opensbi/platform/qemu/sifive_u/platform.c A payloads/external/opensbi/platform/qemu/virt/config.mk A payloads/external/opensbi/platform/qemu/virt/objects.mk A payloads/external/opensbi/platform/qemu/virt/platform.c A payloads/external/opensbi/platform/sifive/fu540/HiFiveUnleashed-MicroSemi-Expansion.dts A payloads/external/opensbi/platform/sifive/fu540/config.mk A payloads/external/opensbi/platform/sifive/fu540/objects.mk A payloads/external/opensbi/platform/sifive/fu540/platform.c A payloads/external/opensbi/platform/template/config.mk A payloads/external/opensbi/platform/template/objects.mk A payloads/external/opensbi/platform/template/platform.c A payloads/external/opensbi/scripts/create-binary-archive.sh 129 files changed, 20,462 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32393/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Gerrit-Change-Number: 32393 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/external/opensbi: fix to boot for fu540
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32395 Change subject: payloads/external/opensbi: fix to boot for fu540 ...................................................................... payloads/external/opensbi: fix to boot for fu540 1. Fix link address to prevent conflict with coreboot 2. Correct source fdt alignment to prevent copy errors Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/external/opensbi/firmware/fw_base.S M payloads/external/opensbi/platform/sifive/fu540/config.mk 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32395/1 diff --git a/payloads/external/opensbi/firmware/fw_base.S b/payloads/external/opensbi/firmware/fw_base.S index 3bf7c6a..ffd9878 100644 --- a/payloads/external/opensbi/firmware/fw_base.S +++ b/payloads/external/opensbi/firmware/fw_base.S @@ -113,7 +113,7 @@ */ beqz a1, _fdt_reloc_done /* Mask values in a3 and a4 */ - li a3, ~0xf + li a3, ~(__SIZEOF_POINTER__ - 1) li a4, 0xff /* t1 = destination FDT start address */ add s0, a0, zero diff --git a/payloads/external/opensbi/platform/sifive/fu540/config.mk b/payloads/external/opensbi/platform/sifive/fu540/config.mk index 352c156..18a2c37 100644 --- a/payloads/external/opensbi/platform/sifive/fu540/config.mk +++ b/payloads/external/opensbi/platform/sifive/fu540/config.mk @@ -19,13 +19,13 @@ PLATFORM_SYS_CLINT=y # Blobs to build -FW_TEXT_START=0x80000000 +FW_TEXT_START=0x82000000 FW_JUMP=y -FW_JUMP_ADDR=0x80200000 -FW_JUMP_FDT_ADDR=0x82200000 +FW_JUMP_ADDR=0x82200000 +FW_JUMP_FDT_ADDR=0x84200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 -FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT_ADDR=0x84200000 # External Libraries to include PLATFORM_INCLUDE_LIBFDT=y -- To view, visit https://review.coreboot.org/c/coreboot/+/32395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Gerrit-Change-Number: 32395 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/fsp_broadwell_de: Configure serial port UPDs correctly
by Matt DeVillier (Code Review) 28 Jul '19

28 Jul '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33452 Change subject: soc/fsp_broadwell_de: Configure serial port UPDs correctly ...................................................................... soc/fsp_broadwell_de: Configure serial port UPDs correctly The SerialPortConfigure UPD (among others) was being left unconfigured when the SoC's integrated UART was not used, leading to serial output via an SIO-attached UART being disabled upon FSP init. Ensure that all serial-related UPDs are set correctly regardless of Kconfig options selected. Test: Boot BDE-based board and verify SIO serial output continues past FSP init Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I634120648afb094be762093b5f9549c241c5668a --- M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33452/1 diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index edb313e..63f9a74 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -64,10 +64,17 @@ UpdData->SerialPortBaudRate = 11; else if (CONFIG(CONSOLE_SERIAL_115200)) UpdData->SerialPortBaudRate = 12; + } else { + UpdData->SerialPortConfigure = 0; + UpdData->SerialPortControllerInit0 = 0; + UpdData->SerialPortControllerInit1 = 0; } - if (!CONFIG(CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) { + UpdData->SerialPortType = 1; + } else { UpdData->SerialPortType = 0; + } UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; -- To view, visit https://review.coreboot.org/c/coreboot/+/33452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634120648afb094be762093b5f9549c241c5668a Gerrit-Change-Number: 33452 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/fintek: Add f81803a
by Richard Spiegel (Code Review) 26 Jul '19

26 Jul '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33623 Change subject: superio/fintek: Add f81803a ...................................................................... superio/fintek: Add f81803a In preparation for padmelon board, add f81803a plus the capability to control the fan with the superio. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/superio/fintek/Makefile.inc A src/superio/fintek/common/fan_control.h A src/superio/fintek/f81803a/Kconfig A src/superio/fintek/f81803a/Makefile.inc A src/superio/fintek/f81803a/acpi/superio.asl A src/superio/fintek/f81803a/f81803a.h A src/superio/fintek/f81803a/f81803a_hwm.h A src/superio/fintek/f81803a/fan_control.c A src/superio/fintek/f81803a/superio.c 9 files changed, 820 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/33623/1 diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 796e519..db683fd 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,3 +26,4 @@ subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +subdirs-y += f81803a diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h new file mode 100644 index 0000000..8828c4b --- /dev/null +++ b/src/superio/fintek/common/fan_control.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_FAN_CONTROL_H +#define SUPERIO_FINTEK_FAN_CONTROL_H + +#include <stdint.h> +#include <arch/io.h> + +#define EXTERNAL_SENSOR1 1 +#define EXTERNAL_SENSOR2 2 +#define EXTERNAL_SENSOR3 3 +#define EXTERNAL_SENSOR_4 4 +#define TEMP_SENSOR_THERMISTOR 0 +#define TEMP_SENSOR_BJT 1 +#define TEMP_SENSOR_DEFAULT 2 + +#define FAN_TYPE_PWM_PUSH_PULL 0 +#define FAN_TYPE_DAC_POWER 1 +#define FAN_TYPE_PWM_OPEN_DRAIN 2 +#define FAN_TYPE_SET_BY_STRAP 3 +#define FAN_TYPE_PWM_CHECK 1 /* bit 0 must be 0 for PWM */ + +#define FAN_MODE_AUTO_RPM 0 +#define FAN_MODE_AUTO_PWM_DAC 1 +#define FAN_MODE_MANUAL_RPM 2 +#define FAN_MODE_MANUAL_PWM_DAC 3 +#define FAN_MODE_DEFAULT 4 + +#define FAN_PWM_FREQ_23500 0 +#define FAN_PWM_FREQ_11750 1 +#define FAN_PWM_FREQ_5875 2 +#define FAN_PWM_FREQ_220 3 + +#define FAN_TEMP_PECI 0 +#define FAN_TEMP_EXTERNAL_1 1 +#define FAN_TEMP_EXTERNAL_2 2 +#define FAN_TEMP_TSI 4 +#define FAN_TEMP_MXM 5 + +#define FAN_UP_RATE_2HZ 0 +#define FAN_UP_RATE_5HZ 1 +#define FAN_UP_RATE_10HZ 2 +#define FAN_UP_RATE_20HZ 3 +#define FAN_UP_RATE_DEFAULT 4 +#define FAN_UP_RATE_JUMP 8 + +#define FAN_DOWN_RATE_2HZ 0 +#define FAN_DOWN_RATE_5HZ 1 +#define FAN_DOWN_RATE_10HZ 2 +#define FAN_DOWN_RATE_20HZ 3 +#define FAN_DOWN_RATE_DEFAULT 4 +#define FAN_DOWN_RATE_SAME_AS_UP 5 +#define FAN_DOWN_RATE_JUMP 8 + +#define FAN_FOLLOW_STEP 0 +#define FAN_FOLLOW_INTERPOLATION 1 + +#define HWM_STATUS_SUCCESS 0 +#define HWM_STATUS_INVALID_FAN -1 +#define HWM_STATUS_INVALID_TEMP_SOURCE -2 +#define HWM_STATUS_INVALID_TYPE -3 +#define HWM_STATUS_INVALID_MODE -4 +#define HWM_STATUS_INVALID_RATE -5 +#define HWM_STATUS_INVALID_FREQUENCY -6 +#define HWM_STATUS_INVALID_TEMP_SENSOR -7 +#define HWM_STATUS_INVALID_BOUNDARY_VALUE -8 +#define HWM_STATUS_INVALID_SECTION_VALUE -9 +#define HWM_STATUS_BOUNDARY_WRONG_ORDER -20 +#define HWM_STATUS_SECTIONS_WRONG_ORDER -21 +#define HWM_STATUS_WARNING_SENSOR_DISCONECTED 1 +#define HWM_STATUS_WARNING_FAN_NOT_PWM 2 + +/* + * Boundaries order is from highest temp. to lowest. Values from 0 to 127. + * Boundaries should be defined as u8 boundaries[fintek_boundaries_size]. + */ +#define fintek_boundaries_size 4 +/* + * Section defines the duty_cycle/voltage to be used based on where the + * temperature lies with respect to the boundaries. There are 5 sections + * (4 boundaries) and the order must be from highest to lowest. Values + * from 0% to 100%, will be converted internally to percent of 255. + * Sections should be defined as u8 sections[fintek_sections_size]. + */ +#define fintek_sections_size 5 + +int set_sensor_type(u16 base_address, u8 sensor, u8 type); +int set_fan_temperature_source(u16 base_address, u8 fan, u8 source); +int set_fan_type_mode(u16 base_address, u8 fan, u8 type, u8 mode); +int set_pwm_frequency(u16 base_address, u8 fan, u8 frequency); +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections); +int set_fan_speed_change_rate(u16 base_address, u8 fan, u8 rate_up, + u8 rate_down); + +#endif /* SUPERIO_FINTEK_FAN_CONTROL_H */ diff --git a/src/superio/fintek/f81803a/Kconfig b/src/superio/fintek/f81803a/Kconfig new file mode 100644 index 0000000..f1f6ef3 --- /dev/null +++ b/src/superio/fintek/f81803a/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_FINTEK_F81803A + bool + select SUPERIO_FINTEK_COMMON_PRE_RAM + +config SUPERIO_FINTEK_F81803A_FAN_CONTROL + bool + depends on SUPERIO_FINTEK_COMMON_PRE_RAM + default n diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc new file mode 100644 index 0000000..a953b4a --- /dev/null +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c +endif + +romstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A_FAN_CONTROL) += fan_control.c diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl new file mode 100644 index 0000000..7568131 --- /dev/null +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the F81803A SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Not implemented + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0xa ACPI/PME/ERP Partially implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#define F81803A_SHOW_PME +#include <superio/acpi/pnp.asl> + + + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_PME + #undef SUPERIO_PME_LDN + #define SUPERIO_PME_LDN 0x0A + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1 /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(SUPERIO_PME_LDN) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } +#endif + +} diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h new file mode 100644 index 0000000..a5e9329 --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Datasheet: + * - Name: F81803A + */ + +#ifndef SUPERIO_FINTEK_F81803_H +#define SUPERIO_FINTEK_F81803_H + +/* Logical Device Numbers (LDN) */ +#define F81803A_SP1 0x01 /* UART1 */ +#define F81803A_SP2 0x02 /* UART2 */ +#define F81803A_HWM 0x04 /* Hardware Monitor */ +#define F81803A_KBC 0x05 /* Keyboard/Mouse */ +#define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81803A_WDT 0x07 /* Watch Dog Timer */ +#define F81803A_PME 0x0a /* Power Management Events (PME) */ + +/* registers in Fintek F81803A */ +#define LDN_REG 0x07 + +/* Global Control Registers */ +#define CLOCK_SELECT_REG 0x26 +#define FUNC_PROG_SELECT (1<<3) +#define PORT_SELECT_REG 0x27 + +#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ +#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG 0x2C +#define WAKEUP_CONTROL_REG 0x2d + +/* LUN A - PME, ACPI, ERP */ +#define PME_DEVICE_ENABLE_REG 0x30 +#define PME_ENABLE (1<<0) +#define PME_ERP_ENABLE_REG 0xE0 +#define ERP_ENABLE (1<<7) +#define ERP_PME_EN (1<<1) +#define ERP_PSOUT_EN (1<<0) +#define PME_ERP_CONTROL_1_REG 0xE1 +#define PME_ERP_CONTROL_2_REG 0xE2 +#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 +#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 +#define PME_ERP_MODE_SELECT_REG 0xEC +#define PME_EVENT_ENABLE_1_REG 0xF0 +#define PME_EVENT_STATUS_1_REG 0xF1 +#define PME_EVENT_ENABLE_2_REG 0xF2 +#define PME_EVENT_STATUS_2_REG 0xF3 +#define PME_ACPI_CONTROL_1_REG 0xF4 +#define PME_ACPI_CONTROL_2_REG 0xF5 +#define PME_ACPI_CONTROL_3_REG 0xF6 +#define PME_ACPI_CONTROL_4_REG 0xF7 +#define PME_ACPI_CONTROL_5_REG 0xFB +#define PME_ACPI_CONTROL_6_REG 0xFC + +#endif /* SUPERIO_FINTEK_F81803_H */ diff --git a/src/superio/fintek/f81803a/f81803a_hwm.h b/src/superio/fintek/f81803a/f81803a_hwm.h new file mode 100644 index 0000000..2fba52b --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a_hwm.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F81803_HWM_H +#define SUPERIO_FINTEK_F81803_HWM_H + +#define TP_SENSOR_TYPE 0x6b +#define TP_SENSOR1_TYPE_SHIFT 1 +#define TP_SENSOR2_TYPE_SHIFT 2 +#define TP_SENSOR_TYPE_MASK 0x01 +#define TP_DIODE_STATUS 0x6f +#define TP_MMX_OPEN 0x40 +#define TP_PECI_OPEN 0x20 +#define TP_TSI_OPEN 0x10 +#define TP_EXTERNAL_SENSOR2_OPEN 0x04 +#define TP_EXTERNAL_SENSOR1_OPEN 0x02 + +#define FAN_TYPE_REG 0x94 +#define FAN1_TYPE_SHIFT 0 +#define FAN2_TYPE_SHIFT 2 +#define FAN_TYPE_MASK 0x03 +#define FAN_MODE_REG 0x96 +#define FAN1_MODE_SHIFT 0 +#define FAN2_MODE_SHIFT 4 +#define FAN_MODE_MASK 0x07 +#define FAN1_FREQ_SEL_ADD_SHIFT 3 /* FUNC_PROG_SEL = 1 */ +#define FAN2_FREQ_SEL_ADD_SHIFT 4 /* FUNC_PROG_SEL = 1 */ +#define FAN_UP_RATE_REG 0x9a +#define FAN1_UP_RATE_SHIFT 0 +#define FAN2_UP_RATE_SHIFT 2 +#define FAN_UP_RATE_MASK 0x03 +#define FAN_DOWN_RATE_REG 0x9b +#define FAN1_DOWN_RATE_SHIFT 0 +#define FAN2_DOWN_RATE_SHIFT 2 +#define FAN_DOWN_RATE_MASK 0x03 +#define FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT 7 /* FUNC_PROG_SEL = 1 */ +#define FAN_DIRECT_LOAD_EN_SHIFT 6 /* FUNC_PROG_SEL = 1 */ +#define FAN_FAULT_TIME_REG 0x9f +#define FAN_FUNC_PROG_SEL_SHIFT 7 + +#define FAN1_BOUND_TEMP1 0xa6 +#define FAN1_BOUND_TEMP2 0xa7 +#define FAN1_BOUND_TEMP3 0xa8 +#define FAN1_BOUND_TEMP4 0xa9 +#define FAN1_SECTION_SPEED1 0xaa +#define FAN1_SECTION_SPEED2 0xab +#define FAN1_SECTION_SPEED3 0xac +#define FAN1_SECTION_SPEED4 0xad +#define FAN1_SECTION_SPEED5 0xae +#define FAN2_BOUND_TEMP1 0xb6 +#define FAN2_BOUND_TEMP2 0xb7 +#define FAN2_BOUND_TEMP3 0xb8 +#define FAN2_BOUND_TEMP4 0xb9 +#define FAN2_SECTION_SPEED1 0xba +#define FAN2_SECTION_SPEED2 0xbb +#define FAN2_SECTION_SPEED3 0xbc +#define FAN2_SECTION_SPEED4 0xbd +#define FAN2_SECTION_SPEED5 0xbe +#define FAN_DETAIL_SKIP (FAN2_BOUND_TEMP1 - FAN1_BOUND_TEMP1) + +#define FAN1_TMP_MAPPING 0xaf +#define FAN2_TMP_MAPPING 0xbf +#define FAN_TEMP_SEL_HIGH_SHIFT 7 +#define FAN_PWM_FREQ_SEL_SHIFT 6 +#define FAN_INTERPOLATION_SHIFT 4 +#define FAN_JUMP_UP_SHIFT 3 +#define FAN_JUMP_DOWN_SHIFT 2 +#define FAN_TEMP_SEL_LOW_SHIFT 0 +#define FAN_TEMP_SEL_LOW_MASK 0x03 +#define FAN_BIT_MASK 0x01 + +#define STATUS_INVALID_VALUE -1 +#define STATUS_INVALID_ORDER -2 + +#define FIRST_FAN 1 +#define LAST_FAN 2 +#define MAX_DUTY 100 + +#endif /* SUPERIO_FINTEK_F81803_HWM_H */ diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c new file mode 100644 index 0000000..47c8086 --- /dev/null +++ b/src/superio/fintek/f81803a/fan_control.c @@ -0,0 +1,263 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/fan_control.h" +#include "f81803a_hwm.h" + +static void write_hwm_reg(u16 address, u8 index, u8 value) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + outb(value, data_add); +} + +static u8 read_hwm_reg(u16 address, u8 index) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + return inb(data_add); +} + +static void read_and_or_write(u16 address, u8 index, u8 shift, u8 mask, + u8 value) +{ + u8 use_mask, use_value; + u8 temp = read_hwm_reg(address, index); + + use_mask = mask << shift; + use_value = (value & mask) << shift; + temp &= ~use_mask; + temp |= use_value; + write_hwm_reg(address, index, temp); +} + +static inline void set_prog_sel(u16 address, u8 value) +{ + read_and_or_write(address, FAN_FAULT_TIME_REG, FAN_FUNC_PROG_SEL_SHIFT, + FAN_BIT_MASK, value); +} + +static int check_value_seq(u8 *values, u8 count) +{ + u8 last_value = 128; /* max value is 127 */ + u8 current_value, i; + for (i = 0; i < count; i++) { + current_value = values[i]; + if (current_value > 127) + return STATUS_INVALID_VALUE; + if (current_value >= last_value) + return STATUS_INVALID_ORDER; + last_value = current_value; + } + return HWM_STATUS_SUCCESS; +} + +int set_sensor_type(u16 base_address, u8 sensor, u8 type) +{ + u8 sensor_status = read_hwm_reg(base_address, TP_DIODE_STATUS); + if (sensor == TEMP_SENSOR_DEFAULT) + return HWM_STATUS_SUCCESS; + switch (sensor) { + case EXTERNAL_SENSOR1: + if (sensor_status & TP_EXTERNAL_SENSOR1_OPEN) + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + read_and_or_write(base_address, TP_SENSOR_TYPE, + TP_SENSOR1_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + case EXTERNAL_SENSOR2: + if (sensor_status & TP_EXTERNAL_SENSOR2_OPEN) + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + read_and_or_write(base_address, TP_SENSOR_TYPE, + TP_SENSOR2_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + default: + return HWM_STATUS_INVALID_TEMP_SENSOR; + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_temperature_source(u16 base_address, u8 fan, u8 source) +{ + u8 index, high_value, low_value; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + high_value = (source >> 2) & FAN_BIT_MASK; + low_value = source & FAN_TEMP_SEL_LOW_MASK; + read_and_or_write(base_address, index, FAN_TEMP_SEL_HIGH_SHIFT, + FAN_BIT_MASK, high_value); + read_and_or_write(base_address, index, FAN_TEMP_SEL_LOW_SHIFT, + FAN_TEMP_SEL_LOW_MASK, low_value); + return HWM_STATUS_SUCCESS; +} + +int set_fan_type_mode(u16 base_address, u8 fan, u8 type, u8 mode) +{ + u8 shift; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + set_prog_sel(base_address, 0); + if (type < FAN_TYPE_SET_BY_STRAP) { + shift = FAN1_TYPE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_TYPE_SHIFT; + read_and_or_write(base_address, FAN_TYPE_REG, shift, + FAN_TYPE_MASK, type); + } + if (mode < FAN_MODE_DEFAULT) { + shift = FAN1_MODE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_MODE_SHIFT; + read_and_or_write(base_address, FAN_MODE_REG, shift, + FAN_MODE_MASK, mode); + } + return HWM_STATUS_SUCCESS; +} + +int set_pwm_frequency(u16 base_address, u8 fan, u8 frequency) +{ + u8 shift, index, byte; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + byte = read_hwm_reg(base_address, FAN_TYPE_REG); + shift = FAN1_TYPE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_TYPE_SHIFT; + if (((byte >> shift) & FAN_TYPE_PWM_CHECK) == FAN_TYPE_PWM_CHECK) + return HWM_STATUS_WARNING_FAN_NOT_PWM; + set_prog_sel(base_address, 1); + shift = FAN1_FREQ_SEL_ADD_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_FREQ_SEL_ADD_SHIFT; + byte = (frequency >> 1) & FAN_BIT_MASK; + read_and_or_write(base_address, FAN_MODE_REG, shift, FAN_BIT_MASK, + byte); + set_prog_sel(base_address, 0); + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + byte = frequency & FAN_BIT_MASK; + read_and_or_write(base_address, index, FAN_PWM_FREQ_SEL_SHIFT, + FAN_BIT_MASK, byte); + return HWM_STATUS_SUCCESS; +} + +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections) +{ + int status, temp; + u8 i, index, value; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + status = check_value_seq(boundaries, + fintek_boundaries_size); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return HWM_STATUS_INVALID_BOUNDARY_VALUE; + return HWM_STATUS_BOUNDARY_WRONG_ORDER; + } + status = check_value_seq(sections, + fintek_sections_size); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return HWM_STATUS_INVALID_SECTION_VALUE; + return HWM_STATUS_SECTIONS_WRONG_ORDER; + } + index = FAN1_BOUND_TEMP1; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + for (i = 0; i < fintek_boundaries_size; i++) { + value = boundaries[i]; + write_hwm_reg(base_address, index, value); + index++; + } + index = FAN1_SECTION_SPEED1; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + for (i = 0; i < fintek_sections_size; i++) { + value = sections[i]; + if (value > 100) + return HWM_STATUS_INVALID_SECTION_VALUE; + temp = (255 * value) / 100; + value = (u8) (temp & 0x00ff); + write_hwm_reg(base_address, index, value); + index++; + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_speed_change_rate(u16 base_address, u8 fan, u8 rate_up, + u8 rate_down) +{ + u8 shift, index; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + shift = FAN1_UP_RATE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_UP_RATE_SHIFT; + + if (rate_up == FAN_UP_RATE_JUMP) { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 1); + } else { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + if (rate_up < FAN_UP_RATE_DEFAULT) { + read_and_or_write(base_address, FAN_UP_RATE_REG, + shift, FAN_UP_RATE_MASK, rate_up); + } + } + + shift = FAN1_DOWN_RATE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_DOWN_RATE_SHIFT; + if (rate_down == FAN_DOWN_RATE_JUMP) { + read_and_or_write(base_address, index, FAN_JUMP_DOWN_SHIFT, + FAN_BIT_MASK, 1); + } else { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + set_prog_sel(base_address, 1); + if (rate_down < FAN_DOWN_RATE_DEFAULT) { + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + shift, FAN_DOWN_RATE_MASK, rate_down); + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 0); + } + if (rate_down == FAN_DOWN_RATE_SAME_AS_UP) { + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 1); + } + set_prog_sel(base_address, 0); + } + return HWM_STATUS_SUCCESS; +} diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c new file mode 100644 index 0000000..2f78244 --- /dev/null +++ b/src/superio/fintek/f81803a/superio.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81803a.h" + +static void f81803a_pme_init(struct device *dev) +{ + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + /* enable ERP function*/ + /* also set PSIN to generate PSOUT*/ + pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN); + pnp_exit_conf_mode(dev); +} + +static void f81803a_init(struct device *dev) +{ + if (!dev->enabled) + return; + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F81803A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case F81803A_PME: + f81803a_pme_init(dev); + break; + } + +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81803a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81803A_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, + { &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + //{ &ops, F81803A_WDT, PNP_IO0, 0x7f8 }, + { &ops, F81803A_PME, }, +}; + +static void enable_dev(struct device *dev) +{ + printk(BIOS_INFO, "F81803A : %s\n", __func__); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81803a_ops = { + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/33623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8 Gerrit-Change-Number: 33623 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

6 65

Change in ...coreboot[master]: google/kukui: Init SSPM
by Erin Lo (Code Review) 26 Jul '19

26 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31835 Change subject: google/kukui: Init SSPM ...................................................................... google/kukui: Init SSPM Load SSPM firmware and boot up SSPM. BUG=b:80501386 BRANCH=none Test=We can see "sspm is alive" in ATF stage if SSPM enabled and ipi success Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31835/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..807a11d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm.bin +sspm.bin-file := 3rdparty/blobs/mainboard/google/kukui/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..6447223 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/usb.h> static void configure_emmc(void) @@ -41,6 +42,7 @@ { configure_emmc(); configure_usb(); + sspm_init(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Gerrit-Change-Number: 31835 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: crossgcc: Add nasm to toolchain
by Martin Roth (Code Review) 25 Jul '19

25 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33024 Change subject: crossgcc: Add nasm to toolchain ...................................................................... crossgcc: Add nasm to toolchain Tianocore payload uses nasm. Supply it in the coreboot toolchain instead of relying on system version. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 --- M util/crossgcc/Makefile M util/crossgcc/Makefile.inc M util/crossgcc/buildgcc A util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum 4 files changed, 34 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/33024/1 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index a8ea815..e7cee98 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -10,12 +10,12 @@ all all_with_gdb: $(MAKE) build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm all_without_gdb: $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm build_tools: build_gcc build_gdb @@ -43,6 +43,9 @@ build_make: bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) +build_nasm: + bash ./buildgcc -P nasm $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) + ########################################################### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf @@ -86,5 +89,6 @@ .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ + build-nasm \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 8f8257c..0ef6b9c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -23,6 +23,7 @@ @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' @echo ' clang - Build coreboot clang compiler' @echo ' gnumake - Build coreboot make' + @echo ' nasm - Build coreboot nasm' @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' @@ -41,7 +42,7 @@ crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ - jenkins-build-toolchain gnumake + jenkins-build-toolchain gnumake nasm $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 @@ -58,6 +59,9 @@ gnumake: clean-for-update $(MAKE) -C util/crossgcc build_make +nasm: clean-for-update + $(MAKE) -C util/crossgcc build_nasm + $(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) build_iasl diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 327027a..9280032 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -61,6 +61,7 @@ CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.14.2 +NASM_VERSION=2.14.02 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if @@ -82,11 +83,13 @@ CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSIO…" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" CMAKE_ARCHIVE="https://cmake.org/files/v3.14/cmake-${CMAKE_VERSION}.tar.gz" +NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERS…" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CFE_ARCHIVE \ - $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE" + $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE \ + $NASM_ARCHIVE" # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" @@ -107,6 +110,7 @@ CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" MAKE_DIR="make-${MAKE_VERSION}" CMAKE_DIR="cmake-${CMAKE_VERSION}" +NASM_DIR="nasm-${NASM_VERSION}" unset MAKELEVEL MAKEFLAGS @@ -910,6 +914,17 @@ normalize_dirs } +build_NASM() { + CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" + ../${NASM_DIR}/configure --prefix="$TARGETDIR" \ + || touch .failed + # shellcheck disable=SC2086 + $MAKE $JOBS || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + + normalize_dirs +} + print_supported() { case "$PRINTSUPPORTED" in AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; @@ -924,6 +939,7 @@ MPFR|mpfr) printf "%s\n" "$MPFR_VERSION";; PYTHON|python) printf "%s\n" "$PYTHON_VERSION";; MAKE|make) printf "%s\n" "$MAKE_VERSION";; + NASM|nasm) printf "%s\n" "${NASM_VERSION}";; *) printf "Unknown tool %s\n" "$PRINTSUPPORTED";; esac } @@ -1044,8 +1060,12 @@ NAME="CMake" PACKAGES=CMAKE ;; + NASM|nasm) + NAME="NASM" + PACKAGES=NASM + ;; *) - printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; + printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE, and NASM)${NC}\n\n"; exit 1 ;; esac diff --git a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum new file mode 100644 index 0000000..f3b9de9 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum @@ -0,0 +1 @@ +fe098ee4dc9c4c983696c4948e64b23e4098b92b tarballs/nasm-2.14.02.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 Gerrit-Change-Number: 33024 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Upgrade CMake to 3.14.4
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33053 Change subject: crossgcc: Upgrade CMake to 3.14.4 ...................................................................... crossgcc: Upgrade CMake to 3.14.4 Change: "In CMake 3.14.0 through 3.14.3, calling target_link_libraries() to add PRIVATE dependencies to a static library created in another directory (under policy CMP0079 NEW behavior) would incorrectly propagate usage requirements of those dependencies to dependents that link the static library. This has been fixed. The bug also existed in 3.13.0 through 3.13.4 and is fixed in 3.13.5." Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33053/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fd5ce43..e99e1d3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.14.2 +CMAKE_VERSION=3.14.4 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum deleted file mode 100644 index 6369ac3..0000000 --- a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -94ef8e36fa93edaf6f194e0ce0065ea769b3e57c tarballs/cmake-3.14.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum new file mode 100644 index 0000000..c292411 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum @@ -0,0 +1 @@ +c4a25807bf80ccd4219aeb75de9a822c4d07f5b8 tarballs/cmake-3.14.4.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/33053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Gerrit-Change-Number: 33053 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: crossgcc: Upgrade Expat to version 2.2.7
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33825 Change subject: crossgcc: Upgrade Expat to version 2.2.7 ...................................................................... crossgcc: Upgrade Expat to version 2.2.7 Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum A util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33825/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 327027a..ea43bce 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -56,7 +56,7 @@ GDB_VERSION=8.2.1 IASL_VERSION=20190509 PYTHON_VERSION=3.7.2 -EXPAT_VERSION=2.2.6 +EXPAT_VERSION=2.2.7 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 diff --git a/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum deleted file mode 100644 index d214819..0000000 --- a/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -c8947fc3119a797b55485f2f7bdaaeb49cc9df01 tarballs/expat-2.2.6.tar.bz2 diff --git a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum new file mode 100644 index 0000000..77f6272 --- /dev/null +++ b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum @@ -0,0 +1 @@ +9c8a268211e3f1ae31c4d550e5be7708973ec6a6 tarballs/expat-2.2.7.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f Gerrit-Change-Number: 33825 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: crossgcc: Upgrade Python to version 3.7.3
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32077 Change subject: crossgcc: Upgrade Python to version 3.7.3 ...................................................................... crossgcc: Upgrade Python to version 3.7.3 Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.7.2.tar.xz.cksum A util/crossgcc/sum/Python-3.7.3.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32077/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e901c37..1b94c33 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 IASL_VERSION=20190215 -PYTHON_VERSION=3.7.2 +PYTHON_VERSION=3.7.3 EXPAT_VERSION=2.2.6 # CLANG version number CLANG_VERSION=7.0.1 diff --git a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum deleted file mode 100644 index 4519f88..0000000 --- a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c3dc6928516bcb934cf4740461044c79c7c35494 tarballs/Python-3.7.2.tar.xz \ No newline at end of file diff --git a/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum new file mode 100644 index 0000000..10679ac --- /dev/null +++ b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum @@ -0,0 +1 @@ +e3584650a06ae2765da0678176deae9d133f1b3d tarballs/Python-3.7.3.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/32077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Gerrit-Change-Number: 32077 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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