coreboot-gerrit June 2019

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Change in ...libgfxinit[master]: gma i2c: Increase timeout to >100ms
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32729 Change subject: gma i2c: Increase timeout to >100ms ...................................................................... gma i2c: Increase timeout to >100ms At least on the ThinkPad X200s with an oddly strapped (and unused) HDMI1, the GMBUS controller doesn't detect the NAK properly and only times out after around 100ms. Change-Id: I48c2ef94e1449a98a35af6912c43156e4ed08206 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-i2c.adb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/29/32729/1 diff --git a/common/hw-gfx-gma-i2c.adb b/common/hw-gfx-gma-i2c.adb index fe26f1c..bc81734 100644 --- a/common/hw-gfx-gma-i2c.adb +++ b/common/hw-gfx-gma-i2c.adb @@ -225,7 +225,7 @@ Registers.Wait_Set_Mask (Register => GMBUS_Regs (2), Mask => GMBUS2_HARDWARE_READY, - TOut_MS => 55); + TOut_MS => 110); Registers.Read (GMBUS_Regs (2), GMBUS2); Success := (GMBUS2 and GMBUS2_HARDWARE_READY) /= 0 and -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I48c2ef94e1449a98a35af6912c43156e4ed08206 Gerrit-Change-Number: 32729 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...libgfxinit[master]: gma i2c: Try to clear NAK indicator
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32491 Change subject: gma i2c: Try to clear NAK indicator ...................................................................... gma i2c: Try to clear NAK indicator Change-Id: I7df80d8757e1d14e288d9424240e873cf5a5fd29 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-i2c.adb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/91/32491/1 diff --git a/common/hw-gfx-gma-i2c.adb b/common/hw-gfx-gma-i2c.adb index d8cdf44..e5cf010 100644 --- a/common/hw-gfx-gma-i2c.adb +++ b/common/hw-gfx-gma-i2c.adb @@ -251,6 +251,10 @@ (Register => GMBUS_Regs (2), Mask => GMBUS2_GMBUS_ACTIVE); end if; + if (GMBUS2 and GMBUS2_NAK_INDICATOR) /= 0 then + Reset_GMBUS (Success); + Success := False; + end if; end if; Length := Transfered; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7df80d8757e1d14e288d9424240e873cf5a5fd29 Gerrit-Change-Number: 32491 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 7

Change in ...libgfxinit[master]: gma: Publish Read_EDID()
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31454 Change subject: gma: Publish Read_EDID() ...................................................................... gma: Publish Read_EDID() Might be useful in coreboot to read the raw EDID. Change-Id: I13d28a4434de3b0699a3475dd96febfdf75639f0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma-display_probing.ads M common/hw-gfx-gma.ads 3 files changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/54/31454/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index 9f756f6..cd2a452 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -13,7 +13,6 @@ -- with HW.GFX.I2C; -with HW.GFX.EDID; with HW.GFX.GMA.Config; with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.I2C; @@ -56,8 +55,6 @@ (Raw_EDID : out EDID.Raw_EDID_Data; Port : in Active_Port_Type; Success : out Boolean) - with - Post => (if Success then EDID.Valid (Raw_EDID)) is Raw_EDID_Length : GFX.I2C.Transfer_Length := Raw_EDID'Length; begin diff --git a/common/hw-gfx-gma-display_probing.ads b/common/hw-gfx-gma-display_probing.ads index f5cd839..e51de88 100644 --- a/common/hw-gfx-gma-display_probing.ads +++ b/common/hw-gfx-gma-display_probing.ads @@ -12,6 +12,8 @@ -- GNU General Public License for more details. -- +with HW.GFX.EDID; + package HW.GFX.GMA.Display_Probing is @@ -20,6 +22,13 @@ All_Ports : constant Port_List := (DP1, DP2, DP3, HDMI1, HDMI2, HDMI3, Analog, Internal); + procedure Read_EDID + (Raw_EDID : out EDID.Raw_EDID_Data; + Port : in Active_Port_Type; + Success : out Boolean) + with + Post => (if Success then EDID.Valid (Raw_EDID)); + procedure Scan_Ports (Configs : out Pipe_Configs; Ports : in Port_List := All_Ports; diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..d3792a2 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -57,6 +57,8 @@ HDMI2, -- or DVI HDMI3, -- or DVI Analog); + subtype Active_Port_Type is Port_Type + range Port_Type'Succ (Disabled) .. Port_Type'Last; type Cursor_Mode is (No_Cursor, ARGB_Cursor); type Cursor_Size is (Cursor_64x64, Cursor_128x128, Cursor_256x256); @@ -171,9 +173,6 @@ ---------------------------------------------------------------------------- -- Internal representation of a single pipe's configuration - subtype Active_Port_Type is Port_Type - range Port_Type'Succ (Disabled) .. Port_Type'Last; - type GPU_Port is (DIGI_A, DIGI_B, DIGI_C, DIGI_D, DIGI_E, LVDS, VGA); subtype Digital_Port is GPU_Port range DIGI_A .. DIGI_E; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I13d28a4434de3b0699a3475dd96febfdf75639f0 Gerrit-Change-Number: 31454 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in ...libgfxinit[master]: gma: Add support for ULX variants
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31452 Change subject: gma: Add support for ULX variants ...................................................................... gma: Add support for ULX variants On Haswell and Broadwell, the ULX variants differ only in the available CD clock frequencies and, on Haswell, the maximum DP link rate. On newer generations (Skylake+), they differ only in output buffer tuning. Also update the PCI IDs from Haswell to Skylake. Still untested, which was the original reason to skip ULX. Change-Id: I08e6689ff8c0f2d58b51363886d4cab956f44e03 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/haswell/hw-gfx-gma-plls.adb M common/haswell_shared/hw-gfx-gma-connectors-ddi.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads M common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb 5 files changed, 136 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/52/31452/1 diff --git a/common/haswell/hw-gfx-gma-plls.adb b/common/haswell/hw-gfx-gma-plls.adb index 3a91bdd..0450238 100644 --- a/common/haswell/hw-gfx-gma-plls.adb +++ b/common/haswell/hw-gfx-gma-plls.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2015-2016, 2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -12,6 +12,7 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config; with HW.GFX.GMA.PLLs.LCPLL; with HW.GFX.GMA.PLLs.WRPLL; @@ -87,8 +88,13 @@ PLL := Invalid; Success := True; elsif Port_Cfg.Display = DP then - PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth); - Success := True; + if Port_Cfg.DP.Bandwidth <= Config.DP_Max_Link_Rate then + PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth); + Success := True; + else + PLL := Invalid; + Success := False; + end if; else Alloc_Configurable (Port_Cfg.Mode, PLL, Success); end if; diff --git a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb index 88f2b22..ef6d568 100644 --- a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb +++ b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb @@ -298,7 +298,7 @@ procedure Initialize is - Iboost_Value : constant Word32 := 1; + Iboost_Value : constant := Config.DDI_Buffer_Iboost; begin if Config.Has_DDI_Buffer_Trans then declare diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index a922b05..b190a78 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -1,5 +1,5 @@ -- --- Copyright (C) 2015-2018 secunet Security Networks AG +-- Copyright (C) 2015-2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -42,6 +42,8 @@ Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; Has_Presence_Straps : constant Boolean := CPU /= Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; + Is_ULX : constant Boolean := CPU_Var = ULX; + Is_LP : constant Boolean := Is_ULT or Is_ULX; ----- CPU pipe: -------- Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge; @@ -74,7 +76,7 @@ Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell - and not Is_ULT); + and not Is_LP); Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell; @@ -98,13 +100,13 @@ Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell; Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell; Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell - and Is_ULT) or + and Is_LP) or CPU >= Skylake; Has_DDI_PHYs : constant Boolean := CPU = Broxton; Has_DDI_D : constant Boolean := CPU >= Haswell and - not Is_ULT and + not Is_LP and not Has_DDI_PHYs; Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP Has_DDI_D; @@ -122,7 +124,7 @@ Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- - Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or + Has_IPS : constant Boolean := (CPU = Haswell and Is_LP) or CPU = Broadwell; Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell; @@ -220,6 +222,8 @@ ---------------------------------------------------------------------------- + DDI_Buffer_Iboost : constant := (if Is_ULX then 3 else 1); + Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is when Haswell => 6, @@ -233,11 +237,11 @@ Default_CDClk_Freq : constant Frequency_Type := (case CPU is when G45 => 320_000_000, -- unused - when Ironlake | - Haswell | - Broadwell => 450_000_000, + when Ironlake => 450_000_000, when Sandybridge | Ivybridge => 400_000_000, + when Haswell | + Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), when Broxton => 288_000_000, when Skylake => 337_500_000); @@ -248,7 +252,7 @@ Sandybridge | Ivybridge => 125_000_000, when Haswell | - Broadwell => (if Is_ULT then 24_000_000 else 125_000_000), + Broadwell => (if Is_LP then 24_000_000 else 125_000_000), when Broxton => Frequency_Type'First, -- none needed when Skylake => 24_000_000); @@ -286,6 +290,11 @@ ---------------------------------------------------------------------------- + DP_Max_Link_Rate : constant DP_Bandwidth := + (if CPU < Haswell or (CPU = Haswell and Is_ULX) + then DP_Bandwidth_2_7 + else DP_Bandwidth_5_4); + -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D HDMI_Max_Clock_24bpp : constant Frequency_Type := (if CPU >= Haswell then 300_000_000 else 225_000_000); @@ -318,15 +327,50 @@ use type HW.Word16; - function Is_Broadwell_H (Device_Id : Word16) return Boolean is - (Device_Id = 16#1612# or Device_Id = 16#1622# or Device_Id = 16#162a#); + -- GMA PCI IDs: + -- + -- Rather catch too much here than too little, it's + -- mostly used to distinguish generations. Best public + -- reference for these IDs is Linux' i915. + -- + -- Since Sandybridge, bits 4 and 5 encode the compu- + -- tational capabilities and can mostly be ignored. + -- From Haswell on, we have to distinguish between + -- Normal, ULT (U CPU lines) and ULX (Y CPU lines). + function Is_Haswell_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffef#) = 16#0a0e#); + function Is_Haswell_U (Device_Id : Word16) return Boolean is + (((Device_Id and 16#ffc3#) = 16#0a02# or + (Device_Id and 16#ffcf#) = 16#0a0b#) and + not Is_Haswell_Y (Device_Id)); + function Is_Haswell (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc3#) = 16#0402# or + (Device_Id and 16#ffcf#) = 16#040b# or + (Device_Id and 16#ffc3#) = 16#0c02# or + (Device_Id and 16#ffcf#) = 16#0c0b# or + (Device_Id and 16#ffc3#) = 16#0d02# or + (Device_Id and 16#ffcf#) = 16#0d0b#); + + function Is_Broadwell_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#160e#); + function Is_Broadwell_U (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#1606# or + (Device_Id and 16#ffcf#) = 16#160b#); + function Is_Broadwell (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc7#) = 16#1602# or + (Device_Id and 16#ffcf#) = 16#160d#); + + function Is_Skylake_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#190e#); function Is_Skylake_U (Device_Id : Word16) return Boolean is - (Device_Id = 16#1906# or Device_Id = 16#1916# or Device_Id = 16#1923# or - Device_Id = 16#1926# or Device_Id = 16#1927#); + ((Device_Id and 16#ffc9#) = 16#1901# or + (Device_Id and 16#ffcf#) = 16#1906#); + function Is_Skylake (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc7#) = 16#1902# or + (Device_Id and 16#ffcf#) = 16#190b# or + (Device_Id and 16#ffcf#) = 16#190d#); - -- Rather catch too much here than too little, - -- it's only used to distinguish generations. function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant) return Boolean is (case CPU is @@ -335,25 +379,19 @@ when Ironlake => (Device_Id and 16#fff3#) = 16#0042#, when Sandybridge => (Device_Id and 16#ffc2#) = 16#0102#, when Ivybridge => (Device_Id and 16#ffc3#) = 16#0142#, - when Haswell => - (case CPU_Var is - when Normal => (Device_Id and 16#ffc3#) = 16#0402# or - (Device_Id and 16#ffc3#) = 16#0d02#, - when ULT => (Device_Id and 16#ffc3#) = 16#0a02#), - when Broadwell => ((Device_Id and 16#ffc3#) = 16#1602# or - (Device_Id and 16#ffcf#) = 16#160b# or - (Device_Id and 16#ffcf#) = 16#160d#) and - (case CPU_Var is - when Normal => Is_Broadwell_H (Device_Id), - when ULT => not Is_Broadwell_H (Device_Id)), + when Haswell => (case CPU_Var is + when Normal => Is_Haswell (Device_Id), + when ULT => Is_Haswell_U (Device_Id), + when ULX => Is_Haswell_Y (Device_Id)), + when Broadwell => (case CPU_Var is + when Normal => Is_Broadwell (Device_Id), + when ULT => Is_Broadwell_U (Device_Id), + when ULX => Is_Broadwell_Y (Device_Id)), when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, - when Skylake => ((Device_Id and 16#ffc3#) = 16#1902# or - (Device_Id and 16#ffcf#) = 16#190b# or - (Device_Id and 16#ffcf#) = 16#190d# or - (Device_Id and 16#fff9#) = 16#1921#) and - (case CPU_Var is - when Normal => not Is_Skylake_U (Device_Id), - when ULT => Is_Skylake_U (Device_Id))); + when Skylake => (case CPU_Var is + when Normal => Is_Skylake (Device_Id), + when ULT => Is_Skylake_U (Device_Id), + when ULX => Is_Skylake_Y (Device_Id))); function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1f81ece..d9023ad 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -44,7 +44,7 @@ Broxton, Skylake); - type CPU_Variant is (Normal, ULT); + type CPU_Variant is (Normal, ULT, ULX); type Port_Type is (Disabled, diff --git a/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb b/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb index 5e72a3b..6ab755b 100644 --- a/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb +++ b/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2017 secunet Security Networks AG +-- Copyright (C) 2017, 2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -51,6 +51,18 @@ 16#0000_5013#, 16#0000_009f#, 16#0000_0018#, 16#0000_00df#); + Skylake_Y_Trans_EDP : constant Buf_Trans_Array := + (16#0000_0018#, 16#0000_00a8#, + 16#0000_4013#, 16#0000_00ab#, + 16#0000_7011#, 16#0000_00a4#, + 16#0000_9010#, 16#0000_00df#, + 16#0000_0018#, 16#0000_00aa#, + 16#0000_6013#, 16#0000_00a4#, + 16#0000_7011#, 16#0000_009d#, + 16#0000_0018#, 16#0000_00a0#, + 16#0000_6012#, 16#0000_00df#, + 16#0000_0018#, 16#0000_008a#); + Skylake_Trans_DP : constant Buf_Trans_Array := (16#0000_2016#, 16#0000_00a0#, 16#0000_5012#, 16#0000_009b#, @@ -75,6 +87,18 @@ 16#8000_5012#, 16#0000_00c0#, others => 0); + Skylake_Y_Trans_DP : constant Buf_Trans_Array := + (16#0000_0018#, 16#0000_00a2#, + 16#0000_5012#, 16#0000_0088#, + 16#8000_7011#, 16#0000_00cd#, + 16#8000_9010#, 16#0000_00c0#, + 16#0000_0018#, 16#0000_009d#, + 16#8000_5012#, 16#0000_00c0#, + 16#8000_7011#, 16#0000_00c0#, + 16#0000_0018#, 16#0000_0088#, + 16#8000_5012#, 16#0000_00c0#, + others => 0); + Skylake_Trans_HDMI : constant HDMI_Buf_Trans_Array := ((16#0000_0018#, 16#0000_00ac#), (16#0000_5012#, 16#0000_009d#), @@ -88,6 +112,19 @@ (16#8000_3015#, 16#0000_00c0#), (16#8000_0018#, 16#0000_00c0#)); + Skylake_Y_Trans_HDMI : constant HDMI_Buf_Trans_Array := + ((16#0000_0018#, 16#0000_00a1#), + (16#0000_5012#, 16#0000_00df#), + (16#8000_7011#, 16#0000_00cb#), + (16#0000_0018#, 16#0000_00a4#), + (16#0000_0018#, 16#0000_009d#), + (16#0000_4013#, 16#0000_0080#), + (16#8000_6013#, 16#0000_00c0#), + (16#0000_0018#, 16#0000_008a#), + (16#8000_3015#, 16#0000_00c0#), + (16#8000_3015#, 16#0000_00c0#), + (16#8000_0018#, 16#0000_00c0#)); + ---------------------------------------------------------------------------- procedure Translations (Trans : out Buf_Trans_Array; Port : Digital_Port) @@ -101,17 +138,26 @@ else Config.Default_DDI_HDMI_Buffer_Translation); begin Trans := - (if not Config.Is_ULT then + (if Config.Is_ULX then (if DDIA_Low_Voltage_Swing - then Skylake_Trans_EDP - else Skylake_Trans_DP) - else + then Skylake_Y_Trans_EDP + else Skylake_Y_Trans_DP) + elsif Config.Is_ULT then (if DDIA_Low_Voltage_Swing then Skylake_U_Trans_EDP - else Skylake_U_Trans_DP)); + else Skylake_U_Trans_DP) + else + (if DDIA_Low_Voltage_Swing + then Skylake_Trans_EDP + else Skylake_Trans_DP)); if not DDIA_Low_Voltage_Swing then - Trans (18) := Skylake_Trans_HDMI (HDMI_Trans).Trans1; - Trans (19) := Skylake_Trans_HDMI (HDMI_Trans).Trans2; + if Config.Is_ULX then + Trans (18) := Skylake_Y_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Skylake_Y_Trans_HDMI (HDMI_Trans).Trans2; + else + Trans (18) := Skylake_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Skylake_Trans_HDMI (HDMI_Trans).Trans2; + end if; end if; end Translations; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I08e6689ff8c0f2d58b51363886d4cab956f44e03 Gerrit-Change-Number: 31452 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: nb/intel/pineview: Remove dead code in switch
by Jacob Garber (Code Review) 19 Jul '19

19 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33407 Change subject: nb/intel/pineview: Remove dead code in switch ...................................................................... nb/intel/pineview: Remove dead code in switch This switch was likely copy-pasted from the one right above it. However, the MEM_CLOCK_800MHz case isn't needed, since that is explicitly checked and avoided before the while loop. With that gone, only the 667MHz/default case is left, which we don't need to switch over anymore. Change-Id: Idfb9cc27dd8718f627d15ba92a9c74c51c2c1c2d Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1347372 --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 6 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33407/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 72063cb..cefa13c 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -498,28 +498,12 @@ lowcas = lsbp; while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { - switch (freq) { - case MEM_CLOCK_800MHz: - if ((s->dimms[i].spd_data[9] > 0x25) || - (s->dimms[i].spd_data[10] > 0x40)) { - // CAS too fast, lower it - highcas--; - break; - } else { - cas = highcas; - } - break; - case MEM_CLOCK_667MHz: - default: - if ((s->dimms[i].spd_data[9] > 0x30) || - (s->dimms[i].spd_data[10] > 0x45)) { - // CAS too fast, lower it - highcas--; - break; - } else { - cas = highcas; - } - break; + if ((s->dimms[i].spd_data[9] > 0x30) || + (s->dimms[i].spd_data[10] > 0x45)) { + // CAS too fast, lower it + highcas--; + } else { + cas = highcas; } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfb9cc27dd8718f627d15ba92a9c74c51c2c1c2d Gerrit-Change-Number: 33407 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 7

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities.
by Frans Hendriks (Code Review) 19 Jul '19

19 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30826 Change subject: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. ...................................................................... security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. Add function tlcl_getcapability() to return capability, used by measured boot. In function unmarshal_get_capability handling of TPM_CAP_PCRS has been added for TPM2 get capability commands. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 302 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30826/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c4f2608..610a99c 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,4 +1,5 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -122,6 +123,35 @@ uint32_t tlcl_continue_self_test(void); /** + * Issue tpm get capability command + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData); + +/** + * Issue more flexible process command + */ +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, + bool marshal); + +/* + * tlcl_extend command that allows more digests to be passed in at the same + * time + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests); + +/** + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); + +/** * Write [length] bytes of [data] to space at [index]. The TPM error code is * returned. */ @@ -144,7 +174,7 @@ uint32_t tlcl_physical_presence_cmd_enable(void); /** - * Finalize the physical presence settings: sofware PP is enabled, hardware PP + * Finalize the physical presence settings: software PP is enabled, hardware PP * is disabled, and the lifetime lock is set. The TPM error code is returned. */ uint32_t tlcl_finalize_physical_presence(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..87f38e1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,6 +16,12 @@ #include "tss_structures.h" #include "tss_marshaling.h" +static INTERNAL_HASH_INFO mHashInfo[] = { + {TPM_ALG_ERROR, 1}, + {TPM_ALG_SHA1, SHA1_DIGEST_SIZE}, + {TPM_ALG_SHA256, SHA256_DIGEST_SIZE}, +}; + /* * This file provides interface between firmware and TPM2 device. The TPM1.2 * API was copied as is and relevant functions modified to comply with the @@ -53,6 +60,48 @@ return tpm_unmarshal_response(command, &ib); } +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, bool marshal) +{ + struct obuf ob; + struct ibuf ib; + size_t out_size; + size_t in_size; + const uint8_t *sendb; + /* Command/response buffer. */ + static uint8_t cr_buffer[TPM_BUFFER_SIZE] CAR_GLOBAL; + + uint8_t *cr_buffer_ptr = car_get_var_ptr(cr_buffer); + + if (marshal) { + obuf_init(&ob, cr_buffer_ptr, sizeof(cr_buffer)); + if (tpm_marshal_command(command, command_body, &ob) < 0) { + printk(BIOS_ERR, "command %#x\n", command); + return NULL; + } + sendb = obuf_contents(&ob, &out_size); + } else { + sendb = command_body; + out_size = command_size; + } + + in_size = sizeof(cr_buffer); + if (tis_sendrecv(sendb, out_size, cr_buffer_ptr, &in_size)) { + printk(BIOS_ERR, "tpm transaction failed\n"); + return NULL; + } + + ibuf_init(&ib, cr_buffer_ptr, in_size); + + if (response_size) + *response_size = in_size; + + if (marshal) + return tpm_unmarshal_response(command, &ib); + else + return cr_buffer_ptr; +} + static uint32_t tlcl_send_startup(TPM_SU type) { struct tpm2_startup startup; @@ -139,7 +188,7 @@ pcr_ext_cmd.digests.count = 1; pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + sizeof(TPMU_HA)); response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); @@ -151,6 +200,65 @@ return TPM_SUCCESS; } +/* + * Handle multiple digests (SHA1 and SHA256 at the moment) + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests) +{ + struct tpm2_pcr_extend_cmd pcr_ext_cmd; + struct tpm2_response *response; + int i; + + pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; + pcr_ext_cmd.digests.count = in_digests->count; + + printk(BIOS_SPEW, "%s: pcr = %d\n", __func__, pcr_num); + printk(BIOS_SPEW, "%s: in_digests->count = %d\n", __func__, + in_digests->count); + + for (i = 0; i < in_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + in_digests->digests[i].hashAlg; + memcpy((void *) pcr_ext_cmd.digests.digests[i].digest.sha256, + (void *) in_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + + printk(BIOS_SPEW, "%s: in_digests[%d]->hash_alg = 0x%x\n", + __func__, i, in_digests->digests[i].hashAlg); + } + + response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); + + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if (in_digests->count == 1) { + if (in_digests->digests[0].hashAlg == TPM_ALG_ERROR) { + if (in_digests->digests[0].digest.invalidate_pcrs == + 1) { + if (response) { + if ((response->hdr.tpm_code & + ~TPM_RC_N_MASK) == (TPM_RC_P | + TPM_RC_HASH)){ + printk(BIOS_SPEW, "%s:" + " TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + } + } + } + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", + __func__, response ? response->hdr.tpm_code : -1); + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + uint32_t tlcl_finalize_physical_presence(void) { /* Nothing needs to be done with tpm2. */ @@ -178,13 +286,22 @@ uint32_t tlcl_lib_init(void) { uint8_t done = car_get_var(tlcl_init_done); + + printk(BIOS_SPEW, "%s: tlcl_init_done is %d\n", __func__, done); if (done) return VB2_SUCCESS; - if (tis_init()) + printk(BIOS_SPEW, "%s: calling tis_init\n", __func__); + if (tis_init()) { + printk(BIOS_ERR, "%s: tis_init returned error\n", __func__); return VB2_ERROR_UNKNOWN; - if (tis_open()) + } + + printk(BIOS_SPEW, "%s: calling tis_open\n", __func__); + if (tis_open()) { + printk(BIOS_ERR, "%s: tis_open returned error\n", __func__); return VB2_ERROR_UNKNOWN; + } car_set_var(tlcl_init_done, 1); @@ -361,3 +478,61 @@ return TPM_SUCCESS; } + +/* + * Issue the tpm2 get capability command + * + * Please note that the capabilityData is not unmarshalled. + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData) +{ + struct tpm2_get_capability cmd; + struct tpm2_response *response; + size_t response_size; + + cmd.capability = capability; + cmd.property = property; + cmd.propertyCount = propertyCount; + + if (propertyCount > 1) { + printk(BIOS_ERR, "%s: PropertyCount more than one not supported" + " yet\n", __func__); + } + + response = tpm_process_command_ex(TPM2_GetCapability, &cmd, 0, + &response_size, 1); + + if (!response) { + printk(BIOS_ERR, "%s: Command Failed\n", __func__); + return TPM_E_IOERROR; + } + + if (moreData) + *moreData = response->gc.more_data; + memcpy(capabilityData, &response->gc.cd, response_size - + sizeof(TPMI_YES_NO) - sizeof(struct tpm_header)); + return TPM_SUCCESS; +} + +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t index; + + for (index = 0; index < ARRAY_SIZE(mHashInfo); index++) + if (mHashInfo[index].hashAlgo == hashAlgo) + return mHashInfo[index].hashSize; + + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + return 0; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 49ac5e8..b4518d20 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,6 +13,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +84,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } @@ -398,6 +400,22 @@ rc |= ibuf_read_be32(ib, &pp->value); } break; + case TPM_CAP_PCRS: + if (ibuf_read_be32(ib, &gcr->cd.data.assignedPCR.count)) + return -1; + if (gcr->cd.data.assignedPCR.count > ARRAY_SIZE + (gcr->cd.data.assignedPCR.pcrSelections)) { + printk(BIOS_INFO, "%s:%s:%d - %d - too many properties\n", + __FILE__, __func__, __LINE__, + gcr->cd.data.assignedPCR.count); + return -1; + } + for (i = 0; i < gcr->cd.data.assignedPCR.count; i++) { + TPMS_PCR_SELECTION *pp = + gcr->cd.data.assignedPCR.pcrSelections + i; + rc |= ibuf_read(ib, pp, sizeof(TPMS_PCR_SELECTION)); + } + break; default: printk(BIOS_ERR, "%s:%d - unable to unmarshal capability response", @@ -448,12 +466,12 @@ } /* - * Let's ignore the authorisation section. It should be 5 bytes total, + * Let's ignore the authorization section. It should be 5 bytes total, * just confirm that this is the case and report any discrepancy. */ if (ibuf_remaining(ib) != 5) printk(BIOS_ERR, - "%s:%d - unexpected authorisation seciton size %zd\n", + "%s:%d - unexpected authorization section size %zd\n", __func__, __LINE__, ibuf_remaining(ib)); ibuf_oob_drain(ib, ibuf_remaining(ib)); diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 2bac633..e70ae02 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,6 +23,12 @@ #define TPM2_RC_SUCCESS 0 #define TPM2_RC_NV_DEFINED 0x14c +// +// We set this to two here as we only support SHA1 and SHA256 right now. +// Should be updated when additional algorithms are supported +// +#define HASH_COUNT 2 + /* Basic TPM2 types. */ typedef uint16_t TPM_SU; typedef uint16_t TPM_ALG_ID; @@ -36,12 +43,28 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ -#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) -#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) -#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) -#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +// Table 7 - TPM_ALG_ID Constants +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) +#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) +#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) +#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) +#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +// Annex A Algorithm Constants + +// Table 205 - Defines for SHA1 Hash Values +#define SHA1_DIGEST_SIZE 20 +// Table 206 - Defines for SHA256 Hash Values #define SHA256_DIGEST_SIZE 32 +// Table 207 - Defines for SHA384 Hash Values +//#define SHA384_DIGEST_SIZE 48 +// Table 208 - Defines for SHA512 Hash Values +#define SHA512_DIGEST_SIZE 64 +// Table 209 - Defines for SM3_256 Hash Values +//#define SM3_256_DIGEST_SIZE 32 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 @@ -79,6 +102,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +// Table 15 - TPM_RC Constants (Actions) +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 @@ -144,7 +173,9 @@ }; /* Various TPM capability types to use when querying the device. */ +// Table 21 - TPM_CAP Constants typedef uint32_t TPM_CAP; +#define TPM_CAP_PCRS ((TPM_CAP)0x00000005) #define TPM_CAP_TPM_PROPERTIES ((TPM_CAP)0x00000006) typedef TPM_HANDLE TPMI_RH_NV_AUTH; @@ -224,16 +255,37 @@ sizeof(TPMI_YES_NO) - sizeof(TPM_CAP) - sizeof(uint32_t)) #define MAX_TPM_PROPERTIES (MAX_CAP_DATA/sizeof(TPMS_TAGGED_PROPERTY)) +#define IMPLEMENTATION_PCR 24 +#define PLATFORM_PCR 24 + +#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8) +#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8) + /* Somewhat arbitrary, leave enough room for command wrappers. */ #define MAX_NV_BUFFER_SIZE (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - 50) +// Table 81 - TPMS_PCR_SELECTION Structure typedef struct { - uint32_t count; - TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; + TPMI_ALG_HASH hash; + uint8_t sizeofSelect; + uint8_t pcrSelect[PCR_SELECT_MAX]; +} __packed TPMS_PCR_SELECTION; + +// Table 98 - TPML_PCR_SELECTION Structure +typedef struct { + uint32_t count; + TPMS_PCR_SELECTION pcrSelections[HASH_COUNT]; +} __packed TPML_PCR_SELECTION; + +// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure +typedef struct { + uint32_t count; + TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; } TPML_TAGGED_TPM_PROPERTY; typedef union { - TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_PCR_SELECTION assignedPCR; } TPMU_CAPABILITIES; typedef struct { @@ -271,22 +323,30 @@ } TPM2B_MAX_NV_BUFFER; /* - * This is a union, but as of now we support just one digest - sha256, so - * there is just one element. + * This is a union, but as of now we support just sha1 and sha256 */ +// Table 66 - TPMU_HA Union typedef union { - uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t invalidate_pcrs; + uint8_t sha1[SHA1_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; } TPMU_HA; typedef struct { + TPMI_ALG_HASH hashAlgo; + uint16_t hashSize; +} INTERNAL_HASH_INFO; + +typedef struct { TPMI_ALG_HASH hashAlg; TPMU_HA digest; } TPMT_HA; +// Table 96 -- TPML_DIGEST_VALUES Structure <I/O> typedef struct { uint32_t count; - TPMT_HA digests[1]; /* Limit max number of hashes to 1. */ -} TPML_DIGEST_VALUES; + TPMT_HA digests[HASH_COUNT]; +} __packed TPML_DIGEST_VALUES; struct nv_read_response { uint32_t params_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/30826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Gerrit-Change-Number: 30826 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

6 47

Change in ...coreboot[master]: device/oprom: Add vbe return status support as per VBE spec 3.0
by Subrata Banik (Code Review) 18 Jul '19

18 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33737 Change subject: device/oprom: Add vbe return status support as per VBE spec 3.0 ...................................................................... device/oprom: Add vbe return status support as per VBE spec 3.0 Existing coreboot oprom implementation relies on user selected vesa mode through CONFIG_FRAMEBUFFER_VESA_MODE Kconfig option and expects that all oprom might support user selected vesa mode. Take an example: Enabling AMD external radeon PCIE graphics card on ICLRVP with default vesa mode 0x118. Unable to get valid X and Y resolution after executing vbe_get_mode_info() with 0x4118, return data buffer shows 0x0 resolution. It causes further hang while trying to draw bmpblk image at depthcharge. This patch checks for output register AX in all vbe functions(0x3 and 0x4f00/1/2) and list all supported vesa mode by oprom using Function 0x4F00 (return vbe controller information). This information might be useful for user to select correct vesa mode for oprom. TEST=Enabling external pcie based graphics card on ICLRVP Case 1: with unsupported vesa mode 0x118 Now coreboot will show below msg to user to know there is a potential issue with choosen vesa mode and better user know the failure rather going to depthcharge and debug further. Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4118 VBE: Function call invalid with unsupported video mode 0x118! User to select mode from below list - Supported Video Mode list for OpRom are: 0x110 0x111 0x113 0x114 0x116 0x117 0x119 0x11a 0x165 0x166 0x121 0x122 0x123 0x124 0x145 0x146 0x175 0x176 0x1d2 0x1d4 Error: In vbe_get_mode_info function Case 2: with supported vesa mode 0x116 Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4116 VBE: resolution: 1024x768@16 VBE: framebuffer: a0000000 VBE: Setting VESA mode 4116 VGA Option ROM was run Change-Id: Iacd2ce468e038a14424f029df3a0adec3e5fa15c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_asm.S M src/include/vbe.h 3 files changed, 107 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33737/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1..d1c7731 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -221,6 +221,90 @@ return mode_info_valid; } +static int vbe_check_for_failure(void); + +static vbe_info_t vbe_get_ctrl_info(void) +{ + char *buffer = PTR_TO_REAL_MODE(__realmode_buffer); + vbe_info_t info; + u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)buffer) & 0xffff; + realmode_interrupt(0x10, VESA_GET_INFO, 0x0000, 0x0000, 0x0000, + buffer_seg, buffer_adr); + if (vbe_check_for_failure()) + die("\nError: In %s function\n", __func__); + memcpy(&info, buffer, sizeof(vbe_info_t)); + + return info; +} + +static void vbe_opron_list_supported_mode(uint16_t *video_mode_ptr) +{ + uint16_t mode; + printk(BIOS_DEBUG,"Supported Video Mode list for OpRom are:\n"); + do + { + mode = *video_mode_ptr++; + if (mode != 0xffff) + printk(BIOS_DEBUG,"%x\n", mode); + } while (mode != 0xffff); +} + +static void vbe_oprom_supported_mode_list(void) +{ + vbe_info_t info = vbe_get_ctrl_info(); + uint32_t video_mode_ptr = info.video_mode_list[1] << 16 | + info.video_mode_list[0]; + vbe_opron_list_supported_mode((uint16_t *)video_mode_ptr); +} + +/* + * EAX register is used to indicate the completion status upon return from + * VBE function in real mode. + * In x86_asm.S, store EAX into REALMODE_BASE before jumping into protected + * mode. + * If the VBE function completed successfully then 0x0 is returned in the AH + * register. Otherwise the AH register is set with the nature of the failure: + * + *AH == 0x00 : Function call successful + *AH == 0x01: Function call failed + *AH == 0x02: Function is not supported in the current HW configuration + *AH == 0x03: Functio call invalid in current video mode + * + *Return 0 on success else -1 for failure + */ +static int vbe_check_for_failure(void) +{ + uint32_t vbe_return_status; + int status; + vbe_return_status = *((unsigned int*)REALMODE_BASE); + + switch ((vbe_return_status & 0xff00) >> 8) { + case 0x0: + status = 0; + break; + case 1: + printk(BIOS_DEBUG, "VBE: Function call failed!\n"); + status = -1; + break; + case 2: + printk(BIOS_DEBUG, "VBE: Function is not supported!\n"); + status = -1; + break; + case 3: + default: + printk(BIOS_DEBUG, "VBE: Function call invalid with" + " unsupported video mode %x!\n", + CONFIG_FRAMEBUFFER_VESA_MODE); + printk(BIOS_DEBUG, "User to select mode from below list - \n"); + vbe_oprom_supported_mode_list(); + status = -1; + break; + } + + return status; +} + static u8 vbe_get_mode_info(vbe_mode_info_t * mi) { printk(BIOS_DEBUG, "VBE: Getting information about VESA mode %04x\n", @@ -230,20 +314,25 @@ u16 buffer_adr = ((unsigned long)buffer) & 0xffff; realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, 0x0000, buffer_seg, buffer_adr); + if (vbe_check_for_failure()) + die("\nError: In %s function\n", __func__); memcpy(mi->mode_info_block, buffer, sizeof(mi->mode_info_block)); mode_info_valid = 1; + return 0; } static u8 vbe_set_mode(vbe_mode_info_t * mi) { printk(BIOS_DEBUG, "VBE: Setting VESA mode %04x\n", mi->video_mode); - // request linear framebuffer mode + /* request linear framebuffer mode */ mi->video_mode |= (1 << 14); - // request clearing of framebuffer + /* request clearing of framebuffer */ mi->video_mode &= ~(1 << 15); realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, 0x0000, 0x0000, 0x0000, 0x0000); + if (vbe_check_for_failure()) + die("\nError: In %s function\n", __func__); return 0; } @@ -253,6 +342,7 @@ void vbe_set_graphics(void) { mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; + vbe_get_mode_info(&mode_info); unsigned char *framebuffer = (unsigned char *)mode_info.vesa.phys_base_ptr; @@ -288,6 +378,8 @@ delay(2); realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000); + if (vbe_check_for_failure()) + die("\nError: In %s function\n", __func__); } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index 87348cd..ed3f897 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -291,6 +291,13 @@ __intXX_instr = RELOCATED(.) .byte 0xcd, 0x00 /* This becomes intXX */ + /* + * Here is end of real mode call and time to go back to protected mode. + * Before that its better to store current eax into some memory address + * so that context persist in protected mode too. + */ + mov %eax, REALMODE_BASE + /* Ok, the job is done, now go back to protected mode coreboot */ movl %cr0, %eax orl $PE, %eax diff --git a/src/include/vbe.h b/src/include/vbe.h index 2c40d05..fea55f5 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -14,6 +14,10 @@ #define VBE_H #include <boot/coreboot_tables.h> + +/* Lets hope we never have more than 256 video modes. */ +#define MAX_VBE_FRAMEBUFFER_MODE 256 + // these structs are for input from and output to OF typedef struct { u8 display_type; // 0 = NONE, 1 = analog, 2 = digital @@ -41,10 +45,9 @@ u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... + u16 video_mode_list[MAX_VBE_FRAMEBUFFER_MODE]; u16 total_memory; -} vbe_info_t; +} __packed vbe_info_t; typedef struct { u16 mode_attributes; // 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacd2ce468e038a14424f029df3a0adec3e5fa15c Gerrit-Change-Number: 33737 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 43

Change in ...coreboot[master]: vendorcode/amd/pi: Add code for merlinfalcon
by Richard Spiegel (Code Review) 18 Jul '19

18 Jul '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33622 Change subject: vendorcode/amd/pi: Add code for merlinfalcon ...................................................................... vendorcode/amd/pi: Add code for merlinfalcon In preparation to commit code for board padmelon (SOC merlinfalcon), add merlinfalcon specific vendor code. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: Id3341f6a1ef2561a6391d3db8c54f6bdd09b0c0e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/Kconfig M src/vendorcode/amd/pi/Makefile.inc A src/vendorcode/amd/pi/merlinfalcon/AGESA.h A src/vendorcode/amd/pi/merlinfalcon/AMD.h A src/vendorcode/amd/pi/merlinfalcon/Include/Filecode.h A src/vendorcode/amd/pi/merlinfalcon/Include/PlatformMemoryConfiguration.h A src/vendorcode/amd/pi/merlinfalcon/Include/Topology.h A src/vendorcode/amd/pi/merlinfalcon/Makefile.inc A src/vendorcode/amd/pi/merlinfalcon/Porting.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/Family/cpuFamRegisters.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/Table.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/cpuFamilyTranslation.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/cpuRegisters.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/cpuServices.h A src/vendorcode/amd/pi/merlinfalcon/Proc/CPU/heapManager.h A src/vendorcode/amd/pi/merlinfalcon/Proc/Common/AmdFch.h A src/vendorcode/amd/pi/merlinfalcon/Proc/Fch/Common/FchCommonCfg.h A src/vendorcode/amd/pi/merlinfalcon/Proc/Fch/Fch.h A src/vendorcode/amd/pi/merlinfalcon/Proc/Fch/FchPlatform.h A src/vendorcode/amd/pi/merlinfalcon/agesa_headers.h A src/vendorcode/amd/pi/merlinfalcon/binaryPI/AGESA.c A src/vendorcode/amd/pi/merlinfalcon/binaryPI/OptionsIds.h A src/vendorcode/amd/pi/merlinfalcon/binaryPI/gcccar.inc A src/vendorcode/amd/pi/merlinfalcon/check_for_wrapper.h A src/vendorcode/amd/pi/merlinfalcon/gcc-intrin.h 25 files changed, 15,459 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33622/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3341f6a1ef2561a6391d3db8c54f6bdd09b0c0e Gerrit-Change-Number: 33622 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 28

Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges
by Patrick Rudolph (Code Review) 18 Jul '19

18 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32074 Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ...................................................................... nb/intel/sandybridge/acpi: Don't use defines for memory ranges Read the northbridge BARs from device PCI0:0.0. Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl 2 files changed, 22 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32074/1 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 09b8892..44fd36c 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -103,7 +103,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 14, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index dce9f67..93e0722 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include "../sandybridge.h" #include "hostbridge.asl" #include "peg.asl" @@ -27,12 +26,13 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + // Filled by _CRS + Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) + Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) + Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) + Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH #if CONFIG(CHROMEOS_RAMOOPS) @@ -48,6 +48,21 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { + CreateDwordField (PDRS, ^MCHB._BAS, MBR0) + MBR0 = \_SB.PCI0.MCHC.MHBR << 14 + + CreateDwordField (PDRS, ^DMIB._BAS, DBR0) + DBR0 = \_SB.PCI0.MCHC.DMBR << 13 + + CreateDwordField (PDRS, ^EGPB._BAS, EBR0) + EBR0 = \_SB.PCI0.MCHC.DMBR << 12 + + CreateDwordField (PDRS, ^PCIX._BAS, XBR0) + XBR0 = \_SB.PCI0.MCHC.PXBR << 26 + + CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) + XSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Return(PDRS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: mb/*/*/gpio: Use static for const structures
by Peter Lemenkov (Code Review) 18 Jul '19

18 Jul '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33524 Change subject: mb/*/*/gpio: Use static for const structures ...................................................................... mb/*/*/gpio: Use static for const structures Autoport generates these structus as static so let's make it consistent. See also commit 128205fd with Change-Id I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve gpio.c generation"). Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/gpio.c M src/mainboard/asus/p5gc-mx/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c M src/mainboard/google/butterfly/gpio.c M src/mainboard/google/link/gpio.c M src/mainboard/google/parrot/gpio.c M src/mainboard/google/stout/gpio.c M src/mainboard/intel/emeraldlake2/gpio.c M src/mainboard/kontron/ktqm77/gpio.c M src/mainboard/lenovo/l520/gpio.c M src/mainboard/lenovo/s230u/gpio.c M src/mainboard/lenovo/t420s/gpio.c M src/mainboard/lenovo/t430/gpio.c M src/mainboard/lenovo/t430s/variants/t430s/gpio.c M src/mainboard/lenovo/t520/variants/t520/gpio.c M src/mainboard/lenovo/t530/variants/t530/gpio.c M src/mainboard/lenovo/t530/variants/w530/gpio.c M src/mainboard/lenovo/x131e/gpio.c M src/mainboard/lenovo/x1_carbon_gen1/gpio.c M src/mainboard/lenovo/x200/gpio.c M src/mainboard/lenovo/x201/gpio.c M src/mainboard/lenovo/x230/gpio.c M src/mainboard/samsung/lumpy/gpio.c M src/mainboard/samsung/stumpy/gpio.c M src/mainboard/sapphire/pureplatinumh61/gpio.c 25 files changed, 273 insertions(+), 273 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/33524/1 diff --git a/src/mainboard/apple/macbookair4_2/gpio.c b/src/mainboard/apple/macbookair4_2/gpio.c index d92269b..485ca95 100644 --- a/src/mainboard/apple/macbookair4_2/gpio.c +++ b/src/mainboard/apple/macbookair4_2/gpio.c @@ -12,7 +12,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, @@ -117,7 +117,7 @@ .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -152,7 +152,7 @@ .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -187,7 +187,7 @@ .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -222,7 +222,7 @@ .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -257,7 +257,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -292,7 +292,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_HIGH, @@ -327,7 +327,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio32 = GPIO_RESET_PWROK, .gpio33 = GPIO_RESET_PWROK, .gpio34 = GPIO_RESET_PWROK, @@ -362,7 +362,7 @@ .gpio63 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -377,7 +377,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -392,7 +392,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -407,7 +407,7 @@ .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio64 = GPIO_RESET_PWROK, .gpio65 = GPIO_RESET_PWROK, .gpio66 = GPIO_RESET_PWROK, diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c index 55c2b3f..d225ba0 100644 --- a/src/mainboard/asus/p5gc-mx/gpio.c +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio6 = GPIO_MODE_GPIO, .gpio7 = GPIO_MODE_GPIO, @@ -39,7 +39,7 @@ .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio6 = GPIO_DIR_INPUT, .gpio7 = GPIO_DIR_INPUT, @@ -63,7 +63,7 @@ .gpio28 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio11 = GPIO_LEVEL_HIGH, .gpio16 = GPIO_LEVEL_LOW, @@ -76,15 +76,15 @@ .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio13 = GPIO_INVERT, .gpio14 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_NATIVE, .gpio34 = GPIO_MODE_NATIVE, @@ -95,7 +95,7 @@ .gpio39 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -106,7 +106,7 @@ .gpio39 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c index 0c19135..90fd9e4 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_NATIVE, .gpio2 = GPIO_MODE_NATIVE, @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -85,7 +85,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio6 = GPIO_LEVEL_HIGH, .gpio7 = GPIO_LEVEL_LOW, @@ -108,12 +108,12 @@ .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio10 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_GPIO, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -124,7 +124,7 @@ .gpio39 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -135,7 +135,7 @@ .gpio39 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index 2d14699..2630177 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* Unused */ .gpio1 = GPIO_MODE_NONE, /* Unused */ .gpio2 = GPIO_MODE_NONE, /* Unused */ @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NONE, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, /* Unused */ .gpio1 = GPIO_DIR_INPUT, /* Unused */ .gpio2 = GPIO_DIR_INPUT, /* Unused */ @@ -85,7 +85,7 @@ .gpio31 = GPIO_DIR_INPUT, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, /* Unused */ .gpio1 = GPIO_LEVEL_LOW, /* Unused */ .gpio2 = GPIO_LEVEL_LOW, /* Unused */ @@ -120,12 +120,12 @@ .gpio31 = GPIO_LEVEL_LOW, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ .gpio34 = GPIO_MODE_NONE, /* Unused */ @@ -160,7 +160,7 @@ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, /* Native */ .gpio33 = GPIO_DIR_INPUT, /* Input */ .gpio34 = GPIO_DIR_INPUT, /* Unused */ @@ -195,7 +195,7 @@ .gpio63 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, /* Native */ .gpio33 = GPIO_LEVEL_LOW, /* Input */ .gpio34 = GPIO_LEVEL_LOW, /* Unused */ @@ -230,7 +230,7 @@ .gpio63 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, /* Unused */ .gpio65 = GPIO_MODE_NONE, /* Unused */ .gpio66 = GPIO_MODE_NONE, /* Unused */ @@ -245,7 +245,7 @@ .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, /* Unused */ .gpio65 = GPIO_DIR_INPUT, /* Unused */ .gpio66 = GPIO_DIR_INPUT, /* Unused */ @@ -260,7 +260,7 @@ .gpio75 = GPIO_DIR_INPUT, /* Input */ }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, /* Unused */ .gpio65 = GPIO_LEVEL_LOW, /* Unused */ .gpio66 = GPIO_LEVEL_LOW, /* Unused */ diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c index dcd29a3..035cf6d 100644 --- a/src/mainboard/google/link/gpio.c +++ b/src/mainboard/google/link/gpio.c @@ -18,7 +18,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ @@ -35,7 +35,7 @@ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, .gpio5 = GPIO_DIR_INPUT, @@ -52,13 +52,13 @@ .gpio28 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio1 = GPIO_LEVEL_HIGH, .gpio6 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio7 = GPIO_INVERT, .gpio8 = GPIO_INVERT, .gpio12 = GPIO_INVERT, @@ -66,7 +66,7 @@ .gpio15 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ @@ -75,7 +75,7 @@ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio36 = GPIO_DIR_OUTPUT, .gpio41 = GPIO_DIR_INPUT, .gpio42 = GPIO_DIR_INPUT, @@ -84,18 +84,18 @@ .gpio60 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio36 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c index 8ad18f1..359b6ec 100644 --- a/src/mainboard/google/parrot/gpio.c +++ b/src/mainboard/google/parrot/gpio.c @@ -18,7 +18,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* NOT USED */ .gpio1 = GPIO_MODE_NONE, /* NOT USED */ .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ @@ -53,7 +53,7 @@ .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -88,7 +88,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -123,14 +123,14 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio7 = GPIO_INVERT, .gpio8 = GPIO_INVERT, .gpio12 = GPIO_INVERT, .gpio15 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ @@ -139,7 +139,7 @@ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -174,7 +174,7 @@ .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -209,7 +209,7 @@ .gpio63 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ @@ -224,7 +224,7 @@ .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -239,7 +239,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c index 43134ea..014037e 100644 --- a/src/mainboard/google/stout/gpio.c +++ b/src/mainboard/google/stout/gpio.c @@ -18,7 +18,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ .gpio2 = GPIO_MODE_NONE, /* NOT USED */ @@ -53,7 +53,7 @@ .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -86,7 +86,7 @@ .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. @@ -119,13 +119,13 @@ .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio8 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ @@ -160,7 +160,7 @@ .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -190,7 +190,7 @@ .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. @@ -220,7 +220,7 @@ .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ @@ -235,7 +235,7 @@ .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -251,7 +251,7 @@ .gpio72 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c index 36c52e3..90010b9 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.c +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -18,7 +18,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -36,7 +36,7 @@ .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, .gpio5 = GPIO_DIR_INPUT, @@ -50,34 +50,34 @@ .gpio27 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, .gpio48 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, .gpio60 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio48 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c index 05c6657..4b88657 100644 --- a/src/mainboard/kontron/ktqm77/gpio.c +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -23,7 +23,7 @@ * system with vendor supplied firmware. */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ @@ -59,7 +59,7 @@ .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ @@ -94,7 +94,7 @@ .gpio31 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ @@ -129,7 +129,7 @@ .gpio31 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ @@ -164,7 +164,7 @@ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, /* Native */ .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ @@ -199,7 +199,7 @@ .gpio63 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, /* Native */ .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ @@ -234,7 +234,7 @@ .gpio63 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ @@ -249,7 +249,7 @@ .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ @@ -264,7 +264,7 @@ .gpio75 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/l520/gpio.c index 68d0c79..c7818ab 100644 --- a/src/mainboard/lenovo/l520/gpio.c +++ b/src/mainboard/lenovo/l520/gpio.c @@ -16,7 +16,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -42,7 +42,7 @@ .gpio30 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -68,7 +68,7 @@ .gpio30 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, @@ -87,20 +87,20 @@ .gpio30 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, .gpio30 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, .gpio36 = GPIO_MODE_GPIO, @@ -123,7 +123,7 @@ .gpio61 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, @@ -145,7 +145,7 @@ .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, @@ -159,10 +159,10 @@ .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -173,7 +173,7 @@ .gpio71 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -184,7 +184,7 @@ .gpio71 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -193,7 +193,7 @@ .gpio71 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/s230u/gpio.c b/src/mainboard/lenovo/s230u/gpio.c index a0e30c2..31bb6fa 100644 --- a/src/mainboard/lenovo/s230u/gpio.c +++ b/src/mainboard/lenovo/s230u/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, /* POUT1# (from palm sensor 1) */ @@ -47,7 +47,7 @@ .gpio31 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_OUTPUT, .gpio2 = GPIO_DIR_INPUT, @@ -79,7 +79,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, @@ -101,11 +101,11 @@ .gpio30 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio2 = GPIO_INVERT, .gpio4 = GPIO_INVERT, .gpio6 = GPIO_NO_INVERT, @@ -118,10 +118,10 @@ .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, /* PCH_WLBT_OFF_5# (to WLAN mPCIe pin 5) */ /* GPIO34 marked as PCH_BT_ON#, but is native (STP_PCI#) */ .gpio35 = GPIO_MODE_GPIO, /* 3G_DET# (from WWAN/mSATA mPCIe pin 43) */ @@ -148,7 +148,7 @@ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_OUTPUT, @@ -173,7 +173,7 @@ .gpio60 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_HIGH, @@ -194,10 +194,10 @@ .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio68 = GPIO_MODE_GPIO, @@ -208,7 +208,7 @@ .gpio74 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio68 = GPIO_DIR_OUTPUT, @@ -219,7 +219,7 @@ .gpio74 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, @@ -227,7 +227,7 @@ .gpio74 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c index c391577..3058f1a 100644 --- a/src/mainboard/lenovo/t420s/gpio.c +++ b/src/mainboard/lenovo/t420s/gpio.c @@ -12,7 +12,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input @@ -47,7 +47,7 @@ .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,17 +117,17 @@ .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output .gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP .gpio34 = GPIO_MODE_GPIO, // DGFX_VRM_ID - input - HIGH: 1GB / LOW: 2GB @@ -162,7 +162,7 @@ .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -197,7 +197,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -232,7 +232,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, // NC .gpio65 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_NSS - output .gpio66 = GPIO_MODE_NATIVE, // NC @@ -247,7 +247,7 @@ .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -262,7 +262,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c index 2e4897a..4a90179 100644 --- a/src/mainboard/lenovo/t430/gpio.c +++ b/src/mainboard/lenovo/t430/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -37,7 +37,7 @@ .gpio29 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -52,26 +52,26 @@ .gpio27 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio10 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, @@ -91,7 +91,7 @@ .gpio57 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, @@ -105,7 +105,7 @@ .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, @@ -114,10 +114,10 @@ .gpio55 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -128,7 +128,7 @@ .gpio71 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -139,10 +139,10 @@ .gpio71 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c index 56fb578..9adc481 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c @@ -12,7 +12,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,21 +117,21 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -166,7 +166,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -201,7 +201,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -236,7 +236,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -251,7 +251,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -266,7 +266,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t520/variants/t520/gpio.c b/src/mainboard/lenovo/t520/variants/t520/gpio.c index 3a10bd0..a4351bb 100644 --- a/src/mainboard/lenovo/t520/variants/t520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/t520/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMI - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -85,7 +85,7 @@ .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -120,17 +120,17 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio7 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output .gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP .gpio34 = GPIO_MODE_GPIO, // VRAM_SIZE_ID - input - HIGH: 1GB / LOW: 2GB @@ -165,7 +165,7 @@ .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -200,7 +200,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -235,7 +235,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, // NC .gpio65 = GPIO_MODE_NATIVE, // NC .gpio66 = GPIO_MODE_NATIVE, // NC @@ -250,7 +250,7 @@ .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -265,7 +265,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t530/variants/t530/gpio.c b/src/mainboard/lenovo/t530/variants/t530/gpio.c index cc3ace2..cbae7f0 100644 --- a/src/mainboard/lenovo/t530/variants/t530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/t530/gpio.c @@ -12,7 +12,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,7 +117,7 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -152,7 +152,7 @@ .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -187,7 +187,7 @@ .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -222,7 +222,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -257,7 +257,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -292,7 +292,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -307,7 +307,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -322,7 +322,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c index c6a10d1..8eb776b 100644 --- a/src/mainboard/lenovo/t530/variants/w530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c @@ -17,7 +17,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -52,7 +52,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -74,7 +74,7 @@ .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio8 = GPIO_LEVEL_LOW, .gpio10 = GPIO_LEVEL_HIGH, .gpio15 = GPIO_LEVEL_LOW, @@ -84,19 +84,19 @@ .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -131,7 +131,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, @@ -151,7 +151,7 @@ .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, @@ -160,10 +160,10 @@ .gpio55 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -178,7 +178,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -189,10 +189,10 @@ .gpio71 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c index d11b662..e51e9af 100644 --- a/src/mainboard/lenovo/x131e/gpio.c +++ b/src/mainboard/lenovo/x131e/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -40,7 +40,7 @@ .gpio29 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -65,7 +65,7 @@ .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, @@ -84,19 +84,19 @@ .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, @@ -117,7 +117,7 @@ .gpio61 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_OUTPUT, @@ -138,7 +138,7 @@ .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_HIGH, .gpio35 = GPIO_LEVEL_HIGH, @@ -149,10 +149,10 @@ .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -164,7 +164,7 @@ .gpio72 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -176,7 +176,7 @@ .gpio72 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_HIGH, @@ -186,7 +186,7 @@ .gpio72 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c index 9a33841..e5beabc 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c @@ -15,7 +15,7 @@ */ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -85,7 +85,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -120,7 +120,7 @@ .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -155,7 +155,7 @@ .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -190,7 +190,7 @@ .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -225,7 +225,7 @@ .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -260,7 +260,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -295,7 +295,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -330,7 +330,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio32 = GPIO_RESET_PWROK, .gpio33 = GPIO_RESET_PWROK, .gpio34 = GPIO_RESET_PWROK, @@ -365,7 +365,7 @@ .gpio63 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -380,7 +380,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -395,7 +395,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -410,7 +410,7 @@ .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio64 = GPIO_RESET_PWROK, .gpio65 = GPIO_RESET_PWROK, .gpio66 = GPIO_RESET_PWROK, diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/gpio.c index 2da4097..516a3ae 100644 --- a/src/mainboard/lenovo/x200/gpio.c +++ b/src/mainboard/lenovo/x200/gpio.c @@ -13,7 +13,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -35,7 +35,7 @@ .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, @@ -57,7 +57,7 @@ .gpio28 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio9 = GPIO_LEVEL_HIGH, .gpio19 = GPIO_LEVEL_HIGH, .gpio20 = GPIO_LEVEL_HIGH, @@ -66,15 +66,15 @@ .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio8 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio36 = GPIO_MODE_GPIO, @@ -89,7 +89,7 @@ .gpio57 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, @@ -104,7 +104,7 @@ .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, .gpio41 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/x201/gpio.c index 76872ec..ee63f87 100644 --- a/src/mainboard/lenovo/x201/gpio.c +++ b/src/mainboard/lenovo/x201/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -85,7 +85,7 @@ .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -120,7 +120,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, @@ -155,7 +155,7 @@ .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -190,7 +190,7 @@ .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_INVERT, @@ -225,7 +225,7 @@ .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -260,7 +260,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -295,7 +295,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -330,7 +330,7 @@ .gpio63 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, .gpio65 = GPIO_MODE_NATIVE, .gpio66 = GPIO_MODE_NATIVE, @@ -345,7 +345,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -360,7 +360,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/gpio.c index a3e3a75..85d086c 100644 --- a/src/mainboard/lenovo/x230/gpio.c +++ b/src/mainboard/lenovo/x230/gpio.c @@ -16,7 +16,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -51,7 +51,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -86,7 +86,7 @@ .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -121,13 +121,13 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -162,7 +162,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -197,7 +197,7 @@ .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -232,7 +232,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -247,7 +247,7 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -262,7 +262,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 9d07e64..103763d 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -22,7 +22,7 @@ * GPIO SET 1 includes GPIO0 to GPIO31 */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ @@ -57,7 +57,7 @@ .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -92,7 +92,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -127,7 +127,7 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_INVERT, @@ -150,7 +150,7 @@ * GPIO SET 2 includes GPIO32 to GPIO63 */ -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ .gpio34 = GPIO_MODE_NONE, @@ -185,7 +185,7 @@ .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -220,7 +220,7 @@ .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -259,7 +259,7 @@ * GPIO SET 3 includes GPIO64 to GPIO75 */ -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, .gpio65 = GPIO_MODE_NONE, .gpio66 = GPIO_MODE_NONE, @@ -274,7 +274,7 @@ .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -289,7 +289,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -304,7 +304,7 @@ .gpio75 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio38 = GPIO_RESET_RSMRST, .gpio43 = GPIO_RESET_RSMRST, }; diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c index eb04c78..282f816 100644 --- a/src/mainboard/samsung/stumpy/gpio.c +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -22,7 +22,7 @@ * GPIO SET 1 includes GPIO0 to GPIO31 */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ .gpio2 = GPIO_MODE_NONE, @@ -57,7 +57,7 @@ .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -92,7 +92,7 @@ .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -131,7 +131,7 @@ * GPIO SET 2 includes GPIO32 to GPIO63 */ -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ .gpio33 = GPIO_MODE_NONE, .gpio34 = GPIO_MODE_NONE, @@ -166,7 +166,7 @@ .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -201,7 +201,7 @@ .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -240,7 +240,7 @@ * GPIO SET 3 includes GPIO64 to GPIO75 */ -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ .gpio65 = GPIO_MODE_NONE, .gpio66 = GPIO_MODE_NONE, @@ -255,7 +255,7 @@ .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -270,7 +270,7 @@ .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c index 5dbb223..b58e0ed 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gpio.c +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -89,7 +89,7 @@ .gpio29 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio6 = GPIO_RESET_PWROK, .gpio7 = GPIO_RESET_PWROK, .gpio8 = GPIO_RESET_PWROK, @@ -135,7 +135,7 @@ .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio35 = GPIO_RESET_PWROK, .gpio37 = GPIO_RESET_PWROK, .gpio38 = GPIO_RESET_PWROK, @@ -144,22 +144,22 @@ .gpio60 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio68 = GPIO_MODE_GPIO, .gpio69 = GPIO_MODE_GPIO, .gpio72 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio68 = GPIO_DIR_INPUT, .gpio69 = GPIO_DIR_INPUT, .gpio72 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio68 = GPIO_RESET_PWROK, .gpio69 = GPIO_RESET_PWROK, .gpio72 = GPIO_RESET_PWROK, -- To view, visit https://review.coreboot.org/c/coreboot/+/33524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Gerrit-Change-Number: 33524 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019