coreboot-gerrit June 2019

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Change in ...coreboot[master]: drivers/wifi: Add generic WiFi driver
by Karthik Ramasubramanian (Code Review) 13 Jul '19

13 Jul '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33155 to review the following change. Change subject: drivers/wifi: Add generic WiFi driver ...................................................................... drivers/wifi: Add generic WiFi driver Add generic WiFi driver to support common device operations across multiple types of WiFi controller. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables and wakeup GPE information. Ensure that the SSDT table is same after the change. Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/intel/wifi/Kconfig M src/drivers/intel/wifi/chip.h M src/drivers/intel/wifi/wifi.c A src/drivers/wifi/Kconfig A src/drivers/wifi/Makefile.inc A src/drivers/wifi/generic.c A src/drivers/wifi/generic_wifi.h 7 files changed, 295 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33155/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..7cf9391 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -2,6 +2,7 @@ bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 default y if PCIEXP_PLUGIN_SUPPORT + select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index 1b3c2a5..72ff951 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -13,26 +13,13 @@ * GNU General Public License for more details. */ -#ifndef _WIFI_CHIP_H_ -#define _WIFI_CHIP_H_ +#ifndef _INTEL_WIFI_CHIP_H_ +#define _INTEL_WIFI_CHIP_H_ -/* WRDS Spec Revision */ -#define WRDS_REVISION 0x0 - -/* EWRD Spec Revision */ -#define EWRD_REVISION 0x0 - -/* WRDS Domain type */ -#define WRDS_DOMAIN_TYPE_WIFI 0x7 - -/* EWRD Domain type */ -#define EWRD_DOMAIN_TYPE_WIFI 0x7 - -/* WGDS Domain type */ -#define WGDS_DOMAIN_TYPE_WIFI 0x7 +#include "drivers/wifi/generic_wifi.h" struct drivers_intel_wifi_config { - unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned int wake; /* Wake pin for ACPI _PRW */ }; -#endif /* _WIFI_CHIP_H_ */ +#endif /* _INTEL_WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 83cfaa9..546c925 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -15,19 +15,16 @@ * GNU General Public License for more details. */ -#include <arch/acpi_device.h> -#include <arch/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include <elog.h> -#include <sar.h> #include <smbios.h> #include <string.h> -#include <wrdd.h> #include "chip.h" +#include "drivers/wifi/generic_wifi.h" #define PMCS_DR 0xcc #define PME_STS (1 << 15) @@ -65,194 +62,15 @@ } #endif -__weak -int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) -{ - return -1; -} - #if CONFIG(HAVE_ACPI_TABLES) -static void emit_sar_acpi_structures(void) -{ - int i, j, package_size; - struct wifi_sar_limits sar_limits; - struct wifi_sar_delta_table *wgds; - - /* Retrieve the sar limits data */ - if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); - return; - } - - /* - * Name ("WRDS", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * WiFi SAR BIOS, // BIOS SAR Enable/disable - * SAR Table Set // Set#1 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("WRDS"); - acpigen_write_package(2); - acpigen_write_dword(WRDS_REVISION); - /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ - package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(SAR_ENABLE)); - for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) - acpigen_write_byte(sar_limits.sar_limit[0][i]); - acpigen_pop_len(); - acpigen_pop_len(); - - /* - * Name ("EWRD", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * Dynamic SAR Enable, // Dynamic SAR Enable/disable - * Extended SAR sets, // Number of optional SAR table sets - * SAR Table Set, // Set#2 of SAR Table (10 bytes) - * SAR Table Set, // Set#3 of SAR Table (10 bytes) - * SAR Table Set // Set#4 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("EWRD"); - acpigen_write_package(2); - acpigen_write_dword(EWRD_REVISION); - /* - * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' - * + number of bytes for Set#2 & 3 & 4 - */ - package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(DSAR_ENABLE)); - acpigen_write_dword(CONFIG_DSAR_SET_NUM); - for (i = 1; i < NUM_SAR_LIMITS; i++) - for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) - acpigen_write_byte(sar_limits.sar_limit[i][j]); - acpigen_pop_len(); - acpigen_pop_len(); - - - if (!CONFIG(GEO_SAR_ENABLE)) - return; - - /* - * Name ("WGDS", Package() { - * Revision, - * Package() { - * DomainType, // 0x7:WiFi - * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max - * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset - * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max - * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max - * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max - * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max - * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max - * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset - * } - * }) - */ - - wgds = &sar_limits.wgds; - acpigen_write_name("WGDS"); - acpigen_write_package(2); - acpigen_write_dword(wgds->version); - /* Emit 'Domain Type' + - * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) - */ - package_size = sizeof(sar_limits.wgds.group) + 1; - acpigen_write_package(package_size); - acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); - for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { - acpigen_write_byte(wgds->group[i].power_max_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); - acpigen_write_byte(wgds->group[i].power_max_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); - } - - acpigen_pop_len(); - acpigen_pop_len(); -} - static void intel_wifi_fill_ssdt(struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; - const char *path = acpi_device_path(dev->bus->dev); - u32 address; + struct generic_wifi_config generic_config = { + .wake = config->wake, + }; - if (!path || !dev->enabled) - return; - - /* Device */ - acpigen_write_scope(path); - acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_integer("_UID", 0); - if (dev->chip_ops) - acpigen_write_name_string("_DDN", dev->chip_ops->name); - - /* Address */ - address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; - address <<= 16; - address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; - acpigen_write_name_dword("_ADR", address); - - /* Wake capabilities */ - if (config && config->wake) - acpigen_write_PRW(config->wake, 3); - - /* Fill regulatory domain structure */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) { - /* - * Name ("WRDD", Package () { - * WRDD_REVISION, // Revision - * Package () { - * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi - * wifi_regulatory_domain() // Country Identifier - * } - * }) - */ - acpigen_write_name("WRDD"); - acpigen_write_package(2); - acpigen_write_integer(WRDD_REVISION); - acpigen_write_package(2); - acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(wifi_regulatory_domain()); - acpigen_pop_len(); - acpigen_pop_len(); - } - - /* Fill Wifi sar related ACPI structures */ - if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ - - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); -} - -static const char *intel_wifi_acpi_name(const struct device *dev) -{ - return "WIFI"; + generic_wifi_fill_ssdt(dev, &generic_config); } #endif @@ -282,7 +100,7 @@ #endif .ops_pci = &pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = intel_wifi_acpi_name, + .acpi_name = generic_wifi_acpi_name, .acpi_fill_ssdt_generator = intel_wifi_fill_ssdt, #endif }; diff --git a/src/drivers/wifi/Kconfig b/src/drivers/wifi/Kconfig new file mode 100644 index 0000000..966dc55 --- /dev/null +++ b/src/drivers/wifi/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_GENERIC_WIFI + bool + default n + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/wifi/Makefile.inc b/src/drivers/wifi/Makefile.inc new file mode 100644 index 0000000..d37015c --- /dev/null +++ b/src/drivers/wifi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_WIFI) += generic.c diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c new file mode 100644 index 0000000..acf1e45 --- /dev/null +++ b/src/drivers/wifi/generic.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <sar.h> +#include <string.h> +#include <wrdd.h> +#include "generic_wifi.h" + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + +/* WGDS Domain type */ +#define WGDS_DOMAIN_TYPE_WIFI 0x7 + +__weak +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + return -1; +} + +static void emit_sar_acpi_structures(void) +{ + int i, j, package_size; + struct wifi_sar_limits sar_limits; + struct wifi_sar_delta_table *wgds; + + /* Retrieve the sar limits data */ + if (get_wifi_sar_limits(&sar_limits) < 0) { + printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + return; + } + + /* + * Name ("WRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * WiFi SAR BIOS, // BIOS SAR Enable/disable + * SAR Table Set // Set#1 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("WRDS"); + acpigen_write_package(2); + acpigen_write_dword(WRDS_REVISION); + /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ + package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(SAR_ENABLE)); + for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) + acpigen_write_byte(sar_limits.sar_limit[0][i]); + acpigen_pop_len(); + acpigen_pop_len(); + + /* + * Name ("EWRD", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * Dynamic SAR Enable, // Dynamic SAR Enable/disable + * Extended SAR sets, // Number of optional SAR table sets + * SAR Table Set, // Set#2 of SAR Table (10 bytes) + * SAR Table Set, // Set#3 of SAR Table (10 bytes) + * SAR Table Set // Set#4 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("EWRD"); + acpigen_write_package(2); + acpigen_write_dword(EWRD_REVISION); + /* + * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' + * + number of bytes for Set#2 & 3 & 4 + */ + package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); + acpigen_write_dword(CONFIG_DSAR_SET_NUM); + for (i = 1; i < NUM_SAR_LIMITS; i++) + for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) + acpigen_write_byte(sar_limits.sar_limit[i][j]); + acpigen_pop_len(); + acpigen_pop_len(); + + + if (!CONFIG(GEO_SAR_ENABLE)) + return; + + /* + * Name ("WGDS", Package() { + * Revision, + * Package() { + * DomainType, // 0x7:WiFi + * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max + * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset + * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max + * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max + * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max + * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max + * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max + * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset + * } + * }) + */ + + wgds = &sar_limits.wgds; + acpigen_write_name("WGDS"); + acpigen_write_package(2); + acpigen_write_dword(wgds->version); + /* Emit 'Domain Type' + + * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) + */ + package_size = sizeof(sar_limits.wgds.group) + 1; + acpigen_write_package(package_size); + acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); + for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { + acpigen_write_byte(wgds->group[i].power_max_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); + acpigen_write_byte(wgds->group[i].power_max_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + +void generic_wifi_fill_ssdt(struct device *dev, + struct generic_wifi_config *config) +{ + const char *path = acpi_device_path(dev->bus->dev); + u32 address; + + if (!path || !dev->enabled) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + if (dev->chip_ops) + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config && config->wake) + acpigen_write_PRW(config->wake, 3); + + /* Fill regulatory domain structure */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) { + /* + * Name ("WRDD", Package () { + * WRDD_REVISION, // Revision + * Package () { + * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi + * wifi_regulatory_domain() // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); + } + + /* Fill Wifi sar related ACPI structures */ + if (CONFIG(USE_SAR)) + emit_sar_acpi_structures(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); +} + +const char *generic_wifi_acpi_name(const struct device *dev) +{ + return "WIFI"; +} diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h new file mode 100644 index 0000000..fdcf66a --- /dev/null +++ b/src/drivers/wifi/generic_wifi.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GENERIC_WIFI_H_ +#define _GENERIC_WIFI_H_ + +/** + * struct generic_wifi_config - Data structure to contain common wifi config + * @wake: Wake pin for ACPI _PRW + */ +struct generic_wifi_config { + unsigned int wake; +}; + +/** + * wifi_fill_ssdt() - Fill ACPI SSDT table for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * @config: Common wifi config required to fill ACPI SSDT table. + * + * This function implements common device operation to help fill ACPI SSDT + * table for WiFi controller. + */ +void generic_wifi_fill_ssdt(struct device *dev, + struct generic_wifi_config *config); + +/** + * wifi_acpi_name() - Get ACPI name for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * + * This function implements common device operation to get the ACPI name for + * WiFi controller. + * + * Return: string representing the ACPI name for WiFi controller. + */ +const char *generic_wifi_acpi_name(const struct device *dev); + +#endif /* _GENERIC_WIFI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Gerrit-Change-Number: 33155 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add some clang-format options
by HAOUAS Elyes (Code Review) 13 Jul '19

13 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33873 Change subject: Add some clang-format options ...................................................................... Add some clang-format options Change-Id: I19773153c8566631400f7c1a1fbb2e44a1df3f9c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M .clang-format 1 file changed, 58 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33873/1 diff --git a/.clang-format b/.clang-format index 5c8aa3c..1b048ca 100644 --- a/.clang-format +++ b/.clang-format @@ -1,21 +1,58 @@ -BasedOnStyle: LLVM -Language: Cpp -IndentWidth: 8 -UseTab: Always -BreakBeforeBraces: Linux -AllowShortIfStatementsOnASingleLine: false -IndentCaseLabels: false -SortIncludes: false -ContinuationIndentWidth: 8 -ColumnLimit: 96 -AlwaysBreakBeforeMultilineStrings: true -AllowShortLoopsOnASingleLine: false -AllowShortFunctionsOnASingleLine: false -AlignEscapedNewlinesLeft: false -AlignTrailingComments: true -AllowAllParametersOfDeclarationOnNextLine: false -AlignAfterOpenBracket: true -SpaceAfterCStyleCast: false -MaxEmptyLinesToKeep: 2 -BreakBeforeBinaryOperators: NonAssignment -BreakStringLiterals: false +--- +AlignAfterOpenBracket: Align +AlignConsecutiveDeclarations: false +AlignEscapedNewlines: Left +AlignOperands: true +AlignTrailingComments: true +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: true +AllowShortCaseLabelsOnASingleLine: true +AllowShortFunctionsOnASingleLine: Empty +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterReturnType: All +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: false +BasedOnStyle: LLVM +BinPackArguments: false +BinPackParameters: false +BreakBeforeBraces: Linux +BreakBeforeTernaryOperators: false +BreakConstructorInitializers: AfterColon +ColumnLimit: 96 +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: false +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 8 +Cpp11BracedListStyle: true +DisableFormat: false +ExperimentalAutoDetectBinPacking: true +FixNamespaceComments: false +IncludeBlocks: Preserve +IndentCaseLabels: false +IndentPPDirectives: None +IndentWidth: 8 +IndentWrappedFunctionNames: false +KeepEmptyLinesAtTheStartOfBlocks: false +Language: Cpp +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: All +ObjCBlockIndentWidth: 1 +ObjCSpaceBeforeProtocolList: true +PointerAlignment: Right +ReflowComments: true +SortIncludes: false +SortUsingDeclarations: false +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: true +SpaceBeforeAssignmentOperators: true +SpaceBeforeParens: ControlStatements +SpaceInEmptyParentheses: false +SpacesInAngles: true +SpacesInContainerLiterals: false +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp11 +UseTab: Always +... -- To view, visit https://review.coreboot.org/c/coreboot/+/33873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19773153c8566631400f7c1a1fbb2e44a1df3f9c Gerrit-Change-Number: 33873 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Add missing include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 12 Jul '19

12 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33526 Change subject: src: Add missing include <device/pci_ops.h> ...................................................................... src: Add missing include <device/pci_ops.h> Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/fidvid.c M src/northbridge/via/vx900/early_host_bus_ctl.c M src/northbridge/via/vx900/pci_util.c M src/soc/intel/quark/acpi.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/mcp55/early_setup_car.c 8 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/33526/1 diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2c6e08c..c5d523a 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -91,6 +91,7 @@ #include <console/console.h> #include <cpu/amd/msr.h> +#include <device/pci_ops.h> #include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 92bb44d..1ef2944 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <device/pci_ops.h> + #include "early_vx900.h" static void vx900_cpu_bus_preram_setup(void) diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 07a9a71..e6eb91a 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -15,6 +15,7 @@ */ #include <console/console.h> +#include <device/pci_ops.h> #include "vx900.h" diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 2cb5adf..ffcd91f 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -16,6 +16,7 @@ */ #include <console/console.h> +#include <device/pci_ops.h> #include <soc/acpi.h> #include <soc/ramstage.h> diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index eaa47e3..b549c5e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <console/console.h> +#include <device/pci_ops.h> #include <reset.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index a8a38f2..8ea776f7 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <reset.h> #include <southbridge/amd/common/reset.h> #include "bcm5785.h" diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 156c387..ee85109 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <console/console.h> +#include <device/pci_ops.h> #include <reset.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 908cdd5..69d12bf 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <delay.h> #include <console/console.h> +#include <device/pci_ops.h> #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); -- To view, visit https://review.coreboot.org/c/coreboot/+/33526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Gerrit-Change-Number: 33526 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST] udelay() in postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31327 Change subject: [TEST] udelay() in postcar ...................................................................... [TEST] udelay() in postcar Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/postcar.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31327/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..957ca92 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <delay.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -28,6 +29,8 @@ void main(void) { + udelay(1); + late_car_teardown(); console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Gerrit-Change-Number: 31327 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel soc/intel: Fix udelay() for postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31326 Change subject: cpu/intel soc/intel: Fix udelay() for postcar ...................................................................... cpu/intel soc/intel: Fix udelay() for postcar We need tsc_freq_mhz() in postcar stage. Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/broadwell/Makefile.inc 5 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31326/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index c317c09..8a2f960 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,10 +1,12 @@ -ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += ../car/romstage.c +postcar-y += tsc_freq.c + ramstage-y += acpi.c +ramstage-y += haswell_init.c +ramstage-y += tsc_freq.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index ec8643a..73c51dc 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,8 +10,9 @@ subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d193e60..ec08c81 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,8 +17,9 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 1debea9..cb721ea 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,8 +12,9 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c ramstage-y += spi.c smm-y += spi.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index acb71fe..f360b96 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -58,8 +58,9 @@ romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c -ramstage-y += tsc_freq.c +postcar-y += tsc_freq.c romstage-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Gerrit-Change-Number: 31326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Update AC/DC loadline values
by Rizwan Qureshi (Code Review) 11 Jul '19

11 Jul '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33371 Change subject: mb/google/hatch: Update AC/DC loadline values ...................................................................... mb/google/hatch: Update AC/DC loadline values Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33371/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 1123d53..333c0f8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,82 @@ # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms -- To view, visit https://review.coreboot.org/c/coreboot/+/33371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Gerrit-Change-Number: 33371 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: include: Implement abs()
by Patrick Rudolph (Code Review) 11 Jul '19

11 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32501 Change subject: include: Implement abs() ...................................................................... include: Implement abs() There are a few external libraries that make use of this simple function. Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/stdlib.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32501/1 diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 34ef93a..a396a3b 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -11,4 +11,9 @@ /* We never free memory */ static inline void free(void *ptr) {} +static inline int abs(int i) +{ + return i < 0 ? -i : i; +} + #endif /* STDLIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Gerrit-Change-Number: 32501 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/nvidia/ck804: Prevent uninitialized reads
by Jacob Garber (Code Review) 10 Jul '19

10 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33459 Change subject: sb/nvidia/ck804: Prevent uninitialized reads ...................................................................... sb/nvidia/ck804: Prevent uninitialized reads ck804_num counts the number of initialized elements in the busn and io_base arrays, so we can only access the first elements of those if ck804_num is non-zero. Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 137058{1,3} --- M src/southbridge/nvidia/ck804/early_setup_car.c 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33459/1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 156c387..03d34a3 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -355,11 +355,19 @@ } } - printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); + if (ck804_num != 0) { + printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", + ck804_num, busn[0], io_base[0]); + printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", + ck804_num, busn[0], io_base[0]); + printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", + ck804_num, busn[0], io_base[0]); + } else { + printk(BIOS_DEBUG, "No ck804 early setup to do\n"); + } + ck804_early_set_port(ck804_num, busn, io_base); - printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); ck804_early_setup(ck804_num, busn, io_base); - printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); ck804_early_clear_port(ck804_num, busn, io_base); return set_ht_link_ck804(4); -- To view, visit https://review.coreboot.org/c/coreboot/+/33459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8 Gerrit-Change-Number: 33459 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/amd: Move 'static' is at beginning of declaration
by HAOUAS Elyes (Code Review) 10 Jul '19

10 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33674 Change subject: vendorcode/amd: Move 'static' is at beginning of declaration ...................................................................... vendorcode/amd: Move 'static' is at beginning of declaration Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/amd/cimx/sb800/AZALIA.c M src/vendorcode/amd/cimx/sb800/ECfanc.c M src/vendorcode/amd/cimx/sb800/SATA.c M src/vendorcode/amd/cimx/sb800/SBCMN.c M src/vendorcode/amd/cimx/sb800/SBPort.c 5 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33674/1 diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index ccb4f90..1d7d0f9 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -61,7 +61,7 @@ * * */ -const static CODECENTRY AzaliaCodecAlc882Table[] = +static const CODECENTRY AzaliaCodecAlc882Table[] = { {0x14, 0x01014010}, {0x15, 0x01011012}, @@ -84,7 +84,7 @@ * * */ -const static CODECENTRY AzaliaCodecAlc262Table[] = +static const CODECENTRY AzaliaCodecAlc262Table[] = { {0x14, 0x01014010}, {0x15, 0x411111F0}, @@ -106,7 +106,7 @@ * * */ -const static CODECENTRY AzaliaCodecAlc269Table[] = +static const CODECENTRY AzaliaCodecAlc269Table[] = { {0x12, 0x99A30960}, {0x14, 0x99130110}, @@ -129,7 +129,7 @@ * * */ -const static CODECENTRY AzaliaCodecAlc861Table[] = +static const CODECENTRY AzaliaCodecAlc861Table[] = { {0x01, 0x8086C601}, {0x0B, 0x01014110}, @@ -152,7 +152,7 @@ * * */ -const static CODECENTRY AzaliaCodecAlc889Table[] = +static const CODECENTRY AzaliaCodecAlc889Table[] = { {0x11, 0x411111F0}, {0x14, 0x01014010}, @@ -176,7 +176,7 @@ * * */ -const static CODECENTRY AzaliaCodecAd1984Table[] = +static const CODECENTRY AzaliaCodecAd1984Table[] = { {0x11, 0x0221401F}, {0x12, 0x90170110}, @@ -198,7 +198,7 @@ * * */ -const static CODECENTRY FrontPanelAzaliaCodecTableList[] = +static const CODECENTRY FrontPanelAzaliaCodecTableList[] = { {0x19, 0x02A19040}, {0x1b, 0x02214020}, @@ -211,7 +211,7 @@ * * */ -const static CODECTBLLIST azaliaCodecTableList[] = +static const CODECTBLLIST azaliaCodecTableList[] = { {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c index 7e679c9..151d882 100644 --- a/src/vendorcode/amd/cimx/sb800/ECfanc.c +++ b/src/vendorcode/amd/cimx/sb800/ECfanc.c @@ -40,7 +40,7 @@ * * */ -const static UINT8 FunctionNumber[] = +static const UINT8 FunctionNumber[] = { Fun_81, Fun_83, @@ -55,7 +55,7 @@ * * */ -const static UINT8 MaxZone[] = +static const UINT8 MaxZone[] = { 4, 4, @@ -70,7 +70,7 @@ * * */ -const static UINT8 MaxRegister[] = +static const UINT8 MaxRegister[] = { MSG_REG9, MSG_REGB, diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index c2f2162..f9823d8 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -176,7 +176,7 @@ * * */ -const static UINT32 sataIfCodeTable[] = +static const UINT32 sataIfCodeTable[] = { 0x01018F40, //sata class ID of IDE 0x01040040, //sata class ID of RAID @@ -192,7 +192,7 @@ * * */ -const static UINT16 sataDeviceIDTable[] = +static const UINT16 sataDeviceIDTable[] = { 0x4390, //sata device ID of IDE 0x4392, //sata device ID of RAID @@ -208,7 +208,7 @@ * * */ -const static SATAPHYSETTING sataPhyTable[] = +static const SATAPHYSETTING sataPhyTable[] = { {0x3006, 0x0056A607}, {0x2006, 0x00061400}, diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 8e9f0e2..ab203a1 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -83,7 +83,7 @@ * sbEarlyPostByteInitTable - PCI device registers initial during early POST. * */ -const static REG8MASK sbEarlyPostByteInitTable[] = +static const REG8MASK sbEarlyPostByteInitTable[] = { // SMBUS Device (Bus 0, Dev 20, Func 0) {0x00, SMBUS_BUS_DEV_FUN, 0}, @@ -134,7 +134,7 @@ * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. * */ -const static AcpiRegWrite sbPmioEPostInitTable[] = +static const AcpiRegWrite sbPmioEPostInitTable[] = { // HPET workaround {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, @@ -251,7 +251,7 @@ * abTblEntry800 - AB-Link Configuration Table for SB800 * */ -const static ABTBLENTRY abTblEntry800[] = +static const ABTBLENTRY abTblEntry800[] = { // RPR Enable downstream posted transactions to pass non-posted transactions. {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, @@ -297,7 +297,7 @@ * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature * */ -const static ABTBLENTRY SbPcieOrderRule[] = +static const ABTBLENTRY SbPcieOrderRule[] = { // abPostPassNpDownStreamTbl {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c index 048850d..ba6c8f0 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPort.c +++ b/src/vendorcode/amd/cimx/sb800/SBPort.c @@ -49,7 +49,7 @@ /** * sbPorInitPciTable - PCI device registers initial during the power on stage. */ -const static REG8MASK sbPorInitPciTable[] = +static const REG8MASK sbPorInitPciTable[] = { // SATA device {0x00, SATA_BUS_DEV_FUN, 0}, @@ -82,7 +82,7 @@ /** * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. */ -const static AcpiRegWrite sbPmioPorInitTable[] = +static const AcpiRegWrite sbPmioPorInitTable[] = { {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, -- To view, visit https://review.coreboot.org/c/coreboot/+/33674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b Gerrit-Change-Number: 33674 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem: Tidy quickpath_reserved calculation
by Jacob Garber (Code Review) 10 Jul '19

10 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33381 Change subject: nb/intel/nehalem: Tidy quickpath_reserved calculation ...................................................................... nb/intel/nehalem: Tidy quickpath_reserved calculation - Remove unnecessary braces - Move variable assignment out of function call - Do not find lowest bit set of 0, which is undefined - Use unsigned integer when bit shifting Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1229562 --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33381/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 15d6abb..af9e620 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1431,14 +1431,17 @@ memory_map[2] = TOUUD | 1; quickpath_reserved = 0; - { - u32 t; + u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); - gav(t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68)); - if (t & 0x800) - quickpath_reserved = - (1 << find_lowest_bit_set32(t >> 20)); + gav(t); + + if (t & 0x800) { + u32 shift = t >> 20; + if (shift == 0) + die("Quickpath value is 0\n"); + quickpath_reserved = (u32)1 << find_lowest_bit_set32(shift); } + if (memory_remap) TOUUD -= quickpath_reserved; -- To view, visit https://review.coreboot.org/c/coreboot/+/33381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c Gerrit-Change-Number: 33381 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019