Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33621
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
soc/amd/stoneyridge: Add merlinfalcon configuration
In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON_FP4) and modify makefile based on this config parameter.
BUG=b:none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 106 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ba82565..047379c 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,8 +23,14 @@ help AMD Stoney Ridge FT4 support
-if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +config SOC_AMD_MERLINFALCON_FP4 + bool + help + AMD Merlin Falcon FP4 support
+if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON_FP4 + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 @@ -71,6 +77,55 @@ select SSE2 select RTC select SOC_AMD_PSP_SELECTABLE_SMU_FW +endif + +if SOC_AMD_MERLINFALCON_FP4 +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select X86_AMD_FIXED_MTRRS + select ACPI_AMD_HARDWARE_SLEEP_VALUES + select COLLECT_TIMESTAMPS_NO_TSC + select DRIVERS_I2C_DESIGNWARE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_SYNC_LFENCE + select COLLECT_TIMESTAMPS + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_S3 + select C_ENVIRONMENT_BOOTBLOCK + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select HAVE_SMI_HANDLER + select SMM_TSEG + select POSTCAR_STAGE + select POSTCAR_CONSOLE + select SSE2 + select RTC +endif
config VBOOT select VBOOT_SEPARATE_VERSTAGE @@ -135,6 +190,7 @@
config VGA_BIOS_ID string + default "1002,9874" if SOC_AMD_MERLINFALCON_FP4 default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -142,6 +198,7 @@
config VGA_BIOS_FILE string + default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" if SOC_AMD_MERLINFALCON_FP4 default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin"
config S3_VGA_ROM_RUN @@ -190,6 +247,7 @@
config AMD_PUBKEY_FILE string "AMD public Key" + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyMF.bin" if SOC_AMD_MERLINFALCON_FP4 default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin"
config STONEYRIDGE_SATA_MODE @@ -386,4 +444,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored.
-endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON_FP4 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..76c4f09 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -142,7 +142,11 @@
### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y) +FIRMWARE_TYPE=MF +else FIRMWARE_TYPE=ST +endif
###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key @@ -214,7 +218,6 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2)
- $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ @@ -232,6 +235,45 @@ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ $(AMDFWTOOL) + +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ + $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUFIRMWARE2_FN_FILE) \ + $(OPT_SMUSCS_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --output $@ +endif + +ifeq ((CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ @@ -267,6 +309,7 @@ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ +endif
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw @@ -313,4 +356,4 @@
endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
-endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_MERLINFALCON_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33621/1/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/1/src/soc/amd/stoneyridge/Makefile.inc... PS1, Line 276: (( ($(
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 1:
(1 comment)
s
https://review.coreboot.org/#/c/33621/1/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/1/src/soc/amd/stoneyridge/Makefile.inc... PS1, Line 276: ((
($(
Thanks....
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#2).
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
soc/amd/stoneyridge: Add merlinfalcon configuration
In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON_FP4) and modify makefile based on this config parameter.
BUG=b:none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 106 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@83 PS2, Line 83: config CPU_SPECIFIC_OPTIONS Aren't at least half of these selected options common for all the SoCs in this file?
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@83 PS2, Line 83: config CPU_SPECIFIC_OPTIONS
Aren't at least half of these selected options common for all the SoCs in this file?
More like 90%. I just was not sure (it failed on a first attempt) if I can use pre-compiler commands within a single config. Thus I made 2 separate configs with same name where only one is compiled.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@26 PS2, Line 26: _FP4 You could drop the FP4 designation just like in 00660F01. The FT4 Infrastructure Roadmap says it's Models 70-7F, i.e. there's no Merlin Falcon / Carrizo (Models 60-6F) in an FT4. We've never claimed support for AM4 with this family, although it might work with a different PI build. And FWIW if we assumed additional possibilities for supporting additional families/infrastructures, I'd probably start rethinking the options in this file.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@83 PS2, Line 83: config CPU_SPECIFIC_OPTIONS
More like 90%. […]
Is there any difference besides SOC_AMD_PSP_SELECTABLE_SMU_FW? For that, duplicate the item from common/block/psp/Kconfig to this file. Remove the select from the list and use 'if' to change the default to y when building ST. Then remove this block, of course.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@201 PS2, Line 201: 00660F01/VBIOS.bin I would go ahead and duplicate VBIOS.bin into the merlinfalcon directory. The hope is to deprecate the nb//00660F01 once you're done.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 146: MF You changed the filenames from their originals? I thought everything was CZ/BR/ST.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 239: ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y) Is this all so that you can remove --combo-capable? I didn't notice any other differences. Just make an OPT_ assignment for that above and don't create unique sections here.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@26 PS2, Line 26: _FP4
You could drop the FP4 designation just like in 00660F01. […]
Good to know, will drop... though it might have a cascade effect in some other patches.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@83 PS2, Line 83: config CPU_SPECIFIC_OPTIONS
Is there any difference besides SOC_AMD_PSP_SELECTABLE_SMU_FW? For that, duplicate the item from co […]
That's the only difference, so I'll try your suggestion.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Kconfig@201 PS2, Line 201: 00660F01/VBIOS.bin
I would go ahead and duplicate VBIOS.bin into the merlinfalcon directory. […]
I already did that when adding the blobs, I just missed it here. Will fix.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 146: MF
You changed the filenames from their originals? I thought everything was CZ/BR/ST.
Yes, I did, though I could have used CZ. Mostly because of the 2 fake _FN files, I wanted them on a separate folder and trully identify them as merlinfalcon only. However, with a different change you sugested on a different patch, this might not be the case anymore... if it all goes as expected, I'll make these files back to CZ.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 239: ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y)
Is this all so that you can remove --combo-capable? I didn't notice any other differences. […]
Could you explain better? Not sure what you are saying here.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 146: MF
Yes, I did, though I could have used CZ. […]
BTW you might want to force the FILE_ variables for the fanless SKUs to be empty assignments. Then add_opt_prefix will generate and empty argument string.
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 239: ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y)
Could you explain better? Not sure what you are saying here.
Somewhere above, add a variable assignment that depends on the device, e.g.
ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable endif
Then replace --combo-capable in the amdfwtool arguments with $(OPT_COMBOCAPABLE).
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 146: MF
BTW you might want to force the FILE_ variables for the fanless SKUs to be empty assignments. […]
I figured out a different way, with ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
https://review.coreboot.org/#/c/33621/2/src/soc/amd/stoneyridge/Makefile.inc... PS2, Line 239: ifeq ($(CONFIG_SOC_AMD_MERLINFALCON_FP4),y)
Somewhere above, add a variable assignment that depends on the device, e.g. […]
Seems to work, thanks.
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#3).
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
soc/amd/stoneyridge: Add merlinfalcon configuration
In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON) and modify makefile based on this config parameter.
BUG=b:none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 45 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/3
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@25 PS3, Line 25: : ## Merlinfalcon only supports FP4. Meh, I could do without this comment. It's already in the help text, and you could embellish that if you feel it's necessary.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@32 PS3, Line 32: config SOC_AMD_PSP_SELECTABLE_SMU_FW Move this item to below CPU_SPECIFIC_OPTIONS somewhere. I'd probably put it just above SOC_AMD_SMU_FANLESS.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@37 PS3, Line 37: Some PSP implementations allow storing SMU firmware into cbfs and : calling the PSP to load the blobs at the proper time. : : The soc/<codename> should select this if its PSP supports the feature : and each mainboard can choose to select an appropriate fanless or : fanned set of blobs. Ask your AMD representative whether your APU : is considered fanless. You're free to override the default help text with anything you want. If MF or ST is selected, then someone checks the help for this option, I think this might be confusing. You could say that some ST implementations support "storing SMU firmware...". And that MF doesn't support it.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc... PS3, Line 204: endif This starts to get confusing. Instead of the additions in lines 166, 168, 171, 174, 196, 198, 201, 203 see if simply inserting at the following at 205 works for you.
ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") SMUFWM_FN_FILE= SMUFIRMWARE2_FN_FILE= endif
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc... PS3, Line 225: ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) You probably won't need this. I believe the add_opt_prefix should assign emptiness to the variables if there's no input file.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@25 PS3, Line 25: : ## Merlinfalcon only supports FP4.
Meh, I could do without this comment. […]
Ok.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@32 PS3, Line 32: config SOC_AMD_PSP_SELECTABLE_SMU_FW
Move this item to below CPU_SPECIFIC_OPTIONS somewhere. […]
Will do.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Kconfig@37 PS3, Line 37: Some PSP implementations allow storing SMU firmware into cbfs and : calling the PSP to load the blobs at the proper time. : : The soc/<codename> should select this if its PSP supports the feature : and each mainboard can choose to select an appropriate fanless or : fanned set of blobs. Ask your AMD representative whether your APU : is considered fanless.
You're free to override the default help text with anything you want. […]
Thanks, will do.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc... PS3, Line 204: endif
This starts to get confusing. […]
I tried, unfortunately no. It would require dummy *_FN images, otherwise build fails.
https://review.coreboot.org/#/c/33621/3/src/soc/amd/stoneyridge/Makefile.inc... PS3, Line 225: ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
You probably won't need this. […]
Will try.
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#4).
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
soc/amd/stoneyridge: Add merlinfalcon configuration
In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON) and modify makefile based on this config parameter.
BUG=b:none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 42 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/4
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33621/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/4//COMMIT_MSG@12 PS4, Line 12: b:none Nit - You don't need the b: if there's no bug.
https://review.coreboot.org/c/coreboot/+/33621/4/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/4/src/soc/amd/stoneyridge/Mak... PS4, Line 250: Remove this blank line. Makefiles don't allow blank lines in the a rule. GNU make might overlook it, but it shouldn't be here.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33621/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/4//COMMIT_MSG@12 PS4, Line 12: b:none
Nit - You don't need the b: if there's no bug.
Just BUG=none. ?
https://review.coreboot.org/c/coreboot/+/33621/4/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/4/src/soc/amd/stoneyridge/Mak... PS4, Line 250:
Remove this blank line. Makefiles don't allow blank lines in the a rule. […]
Will do.
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#5).
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
soc/amd/stoneyridge: Add merlinfalcon configuration
In preparation to add board padmelon, add config parameter for merlinfalcon (SOC_AMD_MERLINFALCON) and modify makefile based on this config parameter.
BUG=none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 62 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/5
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 34: default n Maybe add a help line saying that this option will be removed when the binaries are merged into the blobs repo. You could even add a pointer to the commit for the binaries.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 153: if MERLINFALCON_BINARIES_PRESENT : config VGA_BIOS_FILE : string : default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON : default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" : endif # MERLINFALCON_BINARIES_PRESENT : : if !MERLINFALCON_BINARIES_PRESENT The if clause isn't needed. Just add the one line:
default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && MERLINFALCON_BINARIES_PRESENT
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 210: MERLINFALCON_BINARIES_PRESENT same comment as above.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 347: <codename> Stoneyridge?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 33: bool Add a prompt so this can be enabled & disabled in the menu.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 33: bool
Add a prompt so this can be enabled & disabled in the menu.
Never did a prompt, so was not aware I could. Will investigate how.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 34: default n
Maybe add a help line saying that this option will be removed when the binaries are merged into the […]
Will do.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 153: if MERLINFALCON_BINARIES_PRESENT : config VGA_BIOS_FILE : string : default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON : default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" : endif # MERLINFALCON_BINARIES_PRESENT : : if !MERLINFALCON_BINARIES_PRESENT
The if clause isn't needed. Just add the one line: […]
Will do.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 210: MERLINFALCON_BINARIES_PRESENT
same comment as above.
Will do.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 347: <codename>
Stoneyridge?
Not sure, we are already at soc/stoneyridge. Maybe something like:
If your board is using a version of stoneyridge than it should select an appropriate fanless or fanned...
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33621/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/5//COMMIT_MSG@9 PS5, Line 9: In preparation to add board padmelon, There's no reason to talk about preparing for a board. Instead, make your commit message more descriptive about Merlin Falcon.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 33: bool
Never did a prompt, so was not aware I could. Will investigate how.
Look at line 202.
It seems that something like a symbol name of HAVE_MERLINFALCON_BINARIES would better match other coreboot Kconfig files.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 347: <codename>
Not sure, we are already at soc/stoneyridge. Maybe something like: […]
You forgot to address this comment https://review.coreboot.org/c/coreboot/+/33621/3/src/soc/amd/stoneyridge/Kco...
Perhaps simply make this depends on SOC_AMD_STONEYRIDGE instead of defaulting to a value for MF. (I believe that should work cleanly.)
https://review.coreboot.org/c/coreboot/+/33621/3/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/3/src/soc/amd/stoneyridge/Mak... PS3, Line 204: endif
I tried, unfortunately no. It would require dummy *_FN images, otherwise build fails.
Can you try again please? I tried it before I suggested it to you, and it still builds OK on my side when I test w/Grunt by deleting the ST fanless files.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add merlinfalcon configuration ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33621/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/5//COMMIT_MSG@9 PS5, Line 9: In preparation to add board padmelon,
There's no reason to talk about preparing for a board. […]
Will remove the highlighted.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 33: bool
Look at line 202. […]
Ok, will look and decide.
https://review.coreboot.org/c/coreboot/+/33621/5/src/soc/amd/stoneyridge/Kco... PS5, Line 347: <codename>
You forgot to address this comment https://review.coreboot. […]
Oops... next patch
https://review.coreboot.org/c/coreboot/+/33621/3/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/3/src/soc/amd/stoneyridge/Mak... PS3, Line 204: endif
Can you try again please? I tried it before I suggested it to you, and it still builds OK on my sid […]
Ok, will try again.
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#6).
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
soc/amd/stoneyridge: Add Merlin Falcon configuration
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify makefile based on this config parameter.
BUG=none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 44 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/6
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33621/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/6//COMMIT_MSG@10 PS6, Line 10: makefile modify THE makefile
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... PS6, Line 33: bool Here's how you add the prompt:
bool "Merlinfalcon binaries are present"
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... PS6, Line 327: bool Add a prompt here? Otherwise it will always be y for stoney and N for merlin falcon unless overridden in the mainboard.
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Mak... PS6, Line 197: : ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") Don't you want a build failure if the user wanted to include the file but doesn't have them in the right spot?
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33621/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33621/6//COMMIT_MSG@10 PS6, Line 10: makefile
modify THE makefile
Ok, will do.
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... File src/soc/amd/stoneyridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... PS6, Line 33: bool
Here's how you add the prompt: […]
Thanks, will do.
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Kco... PS6, Line 327: bool
Add a prompt here? Otherwise it will always be y for stoney and N for merlin falcon unless overridd […]
It must always be N for Merlin Falcon. and it was originally selected (thus "Y") for Stoney Ridge. So even before, if a board wanted it to be no then it had to be overridden by mainboard. I think this is fine as is.
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Mak... File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/33621/6/src/soc/amd/stoneyridge/Mak... PS6, Line 197: : ifeq ("$(wildcard $(SMUFWM_FN_FILE))","")
Don't you want a build failure if the user wanted to include the file but doesn't have them in the r […]
No, what I'm doing here is to avoid a much more complicated workaround for Merlin Falcon. Without this change, the Merlin Falcon PSP would need fake _FN.sbin files to avoid a build failure. Merlin Falcon don't have _FN versions for PSP. This solution was suggested by Marshall, replacing a much more complex solution I had before.
Hello Charles Marslett, Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33621
to look at the new patch set (#7).
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
soc/amd/stoneyridge: Add Merlin Falcon configuration
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify the Makefile.inc based on this config parameter.
BUG=none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 44 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/33621/7
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
Patch Set 7: Code-Review+2
LGTM
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33621 )
Change subject: soc/amd/stoneyridge: Add Merlin Falcon configuration ......................................................................
soc/amd/stoneyridge: Add Merlin Falcon configuration
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify the Makefile.inc based on this config parameter.
BUG=none. TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 44 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 78b89e3..3a8fd05 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,7 +23,20 @@ help AMD Stoney Ridge FT4 support
-if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +config SOC_AMD_MERLINFALCON + bool + help + AMD Merlin Falcon FP4 support + +config HAVE_MERLINFALCON_BINARIES + depends on SOC_AMD_MERLINFALCON + bool "Merlinfalcon binaries are present" + default n + help + This config option will be removed once the binaries are merged + to the blobs repo. See 33615. + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON
config CPU_SPECIFIC_OPTIONS def_bool y @@ -68,7 +81,6 @@ select POSTCAR_CONSOLE select SSE2 select RTC - select SOC_AMD_PSP_SELECTABLE_SMU_FW
config VBOOT select VBOOT_SEPARATE_VERSTAGE @@ -133,6 +145,7 @@
config VGA_BIOS_ID string + default "1002,9874" if SOC_AMD_MERLINFALCON default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -140,6 +153,7 @@
config VGA_BIOS_FILE string + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin"
config S3_VGA_ROM_RUN @@ -188,6 +202,7 @@
config AMD_PUBKEY_FILE string "AMD public Key" + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin"
config STONEYRIDGE_SATA_MODE @@ -306,6 +321,17 @@
If unsure, answer 'y'
+config SOC_AMD_PSP_SELECTABLE_SMU_FW + bool + default n if SOC_AMD_MERLINFALCON + default y + help + Some ST implementations allow storing SMU firmware into cbfs and + calling the PSP to load the blobs at the proper time. + + Merlin Falcon does not support it. If you are using 00670F00 SOC, + ask your AMD representative if it supports it or not. + config SOC_AMD_SMU_FANLESS bool depends on SOC_AMD_PSP_SELECTABLE_SMU_FW @@ -384,4 +410,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored.
-endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..150df3a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -142,7 +142,11 @@
### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) +FIRMWARE_TYPE=CZ +else FIRMWARE_TYPE=ST +endif
###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key @@ -191,6 +195,11 @@ SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin endif
+ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") +SMUFWM_FN_FILE= +SMUFIRMWARE2_FN_FILE= +endif + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) @@ -214,6 +223,9 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2)
+ifeq ($(FIRMWARE_TYPE),ST) +OPT_COMBOCAPABLE=--combo-capable +endif
$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ @@ -263,7 +275,7 @@ $(OPT_SMUFIRMWARE2_FILE) \ $(OPT_SMUFIRMWARE2_FN_FILE) \ $(OPT_SMUSCS_FILE) \ - --combo-capable \ + $(OPT_COMBOCAPABLE)\ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ @@ -313,4 +325,4 @@
endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
-endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
-
Angel Pons (Code Review) -
Marshall Dawson (Code Review)
-
Martin Roth (Code Review)
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Richard Spiegel (Code Review)