Change in ...coreboot[master]: sb/intel/common: Add a common interface to set final OPs settings
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33036
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/1
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index bf2a44c..0794bb7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -31,6 +31,8 @@
#include <spi-generic.h>
+#include "spi.h" + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -1041,6 +1043,45 @@ return 0; }
+void spi_finalize_ops(void) +{ + ich_spi_controller *cntlr = &g_cntlr; + u16 spi_opprefix;; + u16 optype = 0; + struct intel_spi_config spi_config = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPTYPE and OPCODE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ + {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ + } + }; + int i; + + if (g_ichspi_lock) + return; + + intel_southbridge_override_spi(&spi_config); + + spi_opprefix = spi_config.opprefixes[0] + | (spi_config.opprefixes[1] << 8); + writew_(spi_opprefix, cntlr->preop); + for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { + optype |= (spi_config.ops[i].type & 3) << (i * 2); + writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + } + writew_(optype, &cntlr->optype); +} + +__weak void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000..fcc5cd8 --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_spi_config *spi_config); + +#endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33036/1/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/1/src/southbridge/intel/common/spi.c@1... PS1, Line 1049: u16 spi_opprefix;; Statements terminations use 1 semicolon
Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/2
Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 2: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 2: Code-Review+1
(3 comments)
There are probably better ways to handle non-default configurations. I remember some discussion, with Stefan I guess, that there are ways to derive the settings from descriptor information.
The thing with retrofitted ports is that you sometimes just don't know what flash chips the board may ship with (or the user may have soldered to it). So without any runtime detection of the chip, this won't always work.
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h File src/southbridge/intel/common/spi.h:
PS2: I think the (function) names should reflect that this is about the `opmenu` or `swseq` and not the SPI controller in general.
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h@3... PS2, Line 36: void intel_southbridge_override_spi(struct intel_spi_config *spi_config); If this is going to be implemented by the mainboard code, it should be named accordingly, imho. e.g. mainboard_override_spi().
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c@1... PS2, Line 1054: /* WRSR: Write Status Register */ aligning these comments would look much better, I guess
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h File src/southbridge/intel/common/spi.h:
PS2:
I think the (function) names should reflect that this is about the `opmenu` […]
ok
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h@3... PS2, Line 36: void intel_southbridge_override_spi(struct intel_spi_config *spi_config);
If this is going to be implemented by the mainboard code, it should […]
There is the sandybridge code that unconditionally sets the opcodes from devicetree and then there what I try to do on lenovo x60 (runtime check for a flash)...
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c@1... PS2, Line 1054: /* WRSR: Write Status Register */
aligning these comments would look much better, I guess
ok
Hello Stefan Tauner, Thomas Heijligen, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33036
to look at the new patch set (#3).
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
(3 comments)
There are probably better ways to handle non-default configurations. I remember some discussion, with Stefan I guess, that there are ways to derive the settings from descriptor information.
The thing with retrofitted ports is that you sometimes just don't know what flash chips the board may ship with (or the user may have soldered to it). So without any runtime detection of the chip, this won't always work.
Maybe just a list of SST flash that use AAI could do the trick?
Hello Stefan Tauner, Thomas Heijligen, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33036
to look at the new patch set (#4).
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c@1... PS4, Line 1054: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c@1... PS4, Line 1057: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c@1... PS4, Line 1058: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c@1... PS4, Line 1060: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/4/src/southbridge/intel/common/spi.c@1... PS4, Line 1081: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 4: Code-Review+1
Looks good, but I need to do more reading on the follow-ups.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c@1... PS5, Line 1079: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c@1... PS5, Line 1082: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c@1... PS5, Line 1083: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c@1... PS5, Line 1085: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/5/src/southbridge/intel/common/spi.c@1... PS5, Line 1106: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
Hello Stefan Tauner, Thomas Heijligen, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33036
to look at the new patch set (#6).
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c@1... PS6, Line 1079: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c@1... PS6, Line 1082: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c@1... PS6, Line 1083: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c@1... PS6, Line 1085: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/6/src/southbridge/intel/common/spi.c@1... PS6, Line 1106: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c@1... PS7, Line 1068: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c@1... PS7, Line 1071: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c@1... PS7, Line 1072: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c@1... PS7, Line 1074: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/7/src/southbridge/intel/common/spi.c@1... PS7, Line 1095: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 8:
(5 comments)
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1068: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1071: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1072: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1074: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1095: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
Hello Stefan Tauner, Thomas Heijligen, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33036
to look at the new patch set (#9).
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 9:
(5 comments)
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c@1... PS9, Line 1068: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c@1... PS9, Line 1071: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c@1... PS9, Line 1072: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c@1... PS9, Line 1074: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/9/src/southbridge/intel/common/spi.c@1... PS9, Line 1095: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 11: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index e9e66dc..8430dc8 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -31,6 +31,8 @@
#include <spi-generic.h>
+#include "spi.h" + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -1048,6 +1050,45 @@ return 0; }
+void spi_finalize_ops(void) +{ + struct ich_spi_controller *cntlr = &g_cntlr; + u16 spi_opprefix; + u16 optype = 0; + struct intel_swseq_spi_config spi_config = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPTYPE and OPCODE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ + {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ + } + }; + int i; + + if (spi_locked()) + return; + + intel_southbridge_override_spi(&spi_config); + + spi_opprefix = spi_config.opprefixes[0] + | (spi_config.opprefixes[1] << 8); + writew_(spi_opprefix, cntlr->preop); + for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { + optype |= (spi_config.ops[i].type & 3) << (i * 2); + writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + } + writew_(optype, &cntlr->optype); +} + +__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) +{ +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000..3b8410c --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_swseq_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); + +#endif
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Martin Roth (Code Review)
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Thomas Heijligen (Code Review)