Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h File src/southbridge/intel/common/spi.h:
PS2:
I think the (function) names should reflect that this is about the `opmenu` […]
ok
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.h@3... PS2, Line 36: void intel_southbridge_override_spi(struct intel_spi_config *spi_config);
If this is going to be implemented by the mainboard code, it should […]
There is the sandybridge code that unconditionally sets the opcodes from devicetree and then there what I try to do on lenovo x60 (runtime check for a flash)...
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/2/src/southbridge/intel/common/spi.c@1... PS2, Line 1054: /* WRSR: Write Status Register */
aligning these comments would look much better, I guess
ok