build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33036 )
Change subject: sb/intel/common: Add a common interface to set final OPs settings ......................................................................
Patch Set 8:
(5 comments)
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1068: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1071: {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1072: {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1074: {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ line over 80 characters
https://review.coreboot.org/#/c/33036/8/src/southbridge/intel/common/spi.c@1... PS8, Line 1095: __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) line over 80 characters