SeaBIOS March 2017

seabios@seabios.org

19 participants
17 discussions

[PATCH 0/3] SeaVGABIOS serial console test
by Kevin O'Connor 05 Sep '17

05 Sep '17

Hi Gerd, I was curious to see what the "sercon" stuff would look like in SeaVGABIOS instead of in SeaBIOS. So, I put together a quick prototype. The code is also at: https://github.com/KevinOConnor/seabios/tree/testing This is just a proof-of-concept thing - I didn't implement any of the useful features you have in your series. Specifically, it doesn't unclutter the serial output, doesn't implement cp437 translations, and doesn't handle multi-byte input. It does does have basic input, … [View More]

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Re: [SeaBIOS] [PATCH 1/4] SeaVGABios/cbvga: Assume VGA compatible GPU in text-mode
by Patrick Rudolph 10 May '17

10 May '17

On Sat Mar 18 02:04:38 CET 2017, Kevin O'Connor wrote: >> Assume the GPU is VGA compatible when running in text-mode. >> Advertise VGA modes using SeaVGABios' stdvga driver. >> running in text mode, even when not advertised. >> >> Allows Windows 7 to boot in 640x480 and 16 colors mode using the >> VgaSave driver. >> Allows Windows 7 to show the loading bar splash screen. >> >> Known issues: >> The palette seems wrong, as colors are … [View More]

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[PATCH 0/9] add support for generic lun enumeration
by Roman Kagan 10 Apr '17

10 Apr '17

A number of SCSI drivers currently only see luns #0 in their targets. This may be a problem when drives have to be assigned bigger lun numbers, e.g. because the storage controllers don't provide enough target numbers to accomodate all drives. (In particular, I'm about to submit a driver for Hyper-V VMBus SCSI controller which is limited to 2 targets only). This series adds generic SCSI lun enumeration (either via REPORT LUNS command or sequentially trying every lun), and makes the respective … [View More]

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issues about keyboard in the safe mode of windows 7
by fulaiyang 31 Mar '17

31 Mar '17

I use the qemu-2.7 and seabios-1.10.1 to start the windows 7 guest. And the xhci controller is passthroughed to the guest. When the safe mode interface of the windows 7 appears, keyboard sometimes doesn't work and I can not choose any mode. I have referred to seabios code about xhci configuration and find that after initializing USB keyboard, the timer ISR will check usb event periodically. Normally, the "xhci_process_events" function can process the keyboard events, but now TRB_C bit of … [View More]

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[PATCH v3] config: Add function to check if fw_cfg exists
by Petr Berky 30 Mar '17

30 Mar '17

It was found qemu_get_present_cpus_count may return impossible number of cpus because of not checking if fw_cfg exists before using it. That may lead to undefined behavior of emulator, in particular Bochs that freezes. Signed-off-by: Petr Berky <petr.berky(a)email.cz> --- src/fw/paravirt.c | 12 +++++++++++- src/fw/paravirt.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 707502d..5b23d78 100644 --- a/src/fw/paravirt.c +… [View More]

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[PATCH] config: Add function to check if fw_cfg exists
by petr.berky＠email.cz 28 Mar '17

28 Mar '17

>From 405de6e571a2bf332452a17ae98f7b3a0613365e Mon Sep 17 00:00:00 2001 From: Petr Berky <petr.berky(a)email.cz> Date: Tue, 14 Mar 2017 20:30:52 +0100 Subject: [PATCH] config: Add function to check if fw_cfg exists It was found qemu_get_present_cpus_count may return impossible number of cpus because of not checking if fw_cfg exists before using it. That may lead to undefined behavior of emulator, in particular Bochs that freezes. Signed-off-by: Petr Berky <petr.berky(a)email.cz&… [View More]

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Bootsplash
by Gert Menke 26 Mar '17

26 Mar '17

Hi, I recently installed Coreboot and SeaBIOS on my Thinkpad X230. After sorting out a little problem with suspend/resume, I am quite happy with it. Now I would like to add a bootsplash image, but SeaBIOS seems unable to find any vesa modes. However, HDT (http://www.hdt-project.org) shows several modes, including the native display resolution (1366x768x32) and the resolution of my bootsplash.bmp (1024x768x32). I am using the proprietary vesa bios blob extracted from the original X230 … [View More]

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[Bochs] [PATCH RFC] shadow: Change order of PCI writes
by petr.berky＠email.cz 25 Mar '17

25 Mar '17

I am working on an issue with SeaBIOS running in Bochs emulator. I found I need to revert SeaBIOS patch d449a11, otherwise Bochs freezes. After the further investigation, I narrowed down the problem to those lines: File: src/fw/shadow.c Function: __make_bios_writable_intel 48 // Write PAM settings back to pci config space 49 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 50 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); File: src/fw/shadow.c … [View More]Function: make_bios_readonly_intel 109 // Write PAM settings back to pci config space 110 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 111 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); What has changed, comparing to the code before patch d449a11 is the order of writes to PAM registers. Before d449a11 the order was: 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x59 After d449a11 the order is : 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f I believe also the 0x58 (DRAMT?) register is written after the patch d449a11 and was not before. I checked, and the registers values after write are exactly the same in both cases (before/after patch). This lead me to think the order of writes matters. So I prepared the patch that restores the old order. I works well and fixes the issue with Bochs. But there is still one think I cannot explain and I hope I can find some help here. If you look on the patch below, you will see I had to use different pci write functions in __make_bios_writable_intel and make_bios_readonly_intel. The only difference in those functions (I think) is the size of data that is written at one call. Still It does not work for me when written some other way. Again, I would appreciate if someone could explain it to me or point me some documentation. Just to summarize, I have two questions: 1. Why the order of pci writes makes a difference here? 2. Why the size of pci writes matters? >From 953c133a6ade49e9148a0734ffefc0fb27c116fb Mon Sep 17 00:00:00 2001 From: Petr Berky <petr.berky(a)email.cz> Date: Sun, 19 Mar 2017 10:14:49 +0100 Subject: [PATCH RFC] shadow: Change order of PCI writes This change solves the problem with Bochs freeze --- src/fw/shadow.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/fw/shadow.c b/src/fw/shadow.c index c80b266..508af20 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -23,6 +23,7 @@ union pamdata_u { u8 data8[8]; + u16 data16[4]; u32 data32[2]; }; @@ -46,8 +47,9 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) pam[0] = 0x30; // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); if (!ram_present) // Copy bios. @@ -107,8 +109,11 @@ make_bios_readonly_intel(u16 bdf, u32 pam0) pam[0] = 0x10; // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data16[2]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 6, pamdata.data8[6]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 7, pamdata.data8[7]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); } static int ShadowBDF = -1; -- 2.11.0 [View Less]

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Re: [SeaBIOS] [PATCH 0/8] SeaVGABIOS improvments for coreboot's framebuffer v2
by Patrick Rudolph 25 Mar '17

25 Mar '17

On Fri, 24 Mar 2017 20:51:56 -0400 Kevin O'Connor <kevin(a)koconnor.net> wrote: > On Fri, Mar 24, 2017 at 05:27:19PM +0100, Patrick Rudolph wrote: > > This series add several fixes to coreboot's framebuffer > > implementation and it main purpose is to fix Microsoft's Windows as > > supported OS. > > > > The series fixes the following issues: > > * Windows shows no image in text-mode > > * Windows NTLDR/bootmgr shows no image in VESA mode > … [View More]

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[PATCH 0/8] SeaVGABIOS improvments for coreboot's framebuffer v2
by Patrick Rudolph 25 Mar '17

25 Mar '17

This series add several fixes to coreboot's framebuffer implementation and it main purpose is to fix Microsoft's Windows as supported OS. The series fixes the following issues: * Windows shows no image in text-mode * Windows NTLDR/bootmgr shows no image in VESA mode * Windows shows no image in VESA mode * Windows legacy Intel VGA driver requires VBT in VGA option ROM * Clear screen broken due to INT 15h replaced by OS I was able to boot Windows with the following configurations: * using … [View More]

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SeaBIOS March 2017