Hardware Reset(From Intel's "64 and IA-32 Architectures Software Developer’s
Manual" (doc 253668-021 October 2006), Volume 3A, Section 9.1.4:)
The first instruction that is fetched and executed following a hardware reset is located
at physical address 0xFFFFFFF0. This address is 16 bytes below the processor’s uppermost
physical address. The EPROM containing the software-initialization code must be located at
The address 0xFFFFFFF0 is beyond the 1-MByte addressable range of the processor while in
real-address mode. The processor is initialized to this starting address as follows. The
CS register has two parts: the visible segment selector part and the hidden base address
part. In real-address mode, the base address is normally formed by shifting the 16-bit
segment selector value 4 bits to the left to produce a 20-bit base address. However,
during a hardware reset, the segment selector in the CS register is loaded with 0xF000 and
the base address is loaded with 0xFFFF0000. The starting address is thus formed by adding
the base address to the value in the EIP register (that is, 0xFFFF0000 + 0xFFF0 =
The first time the CS register is loaded with a new value after a hardware reset, the
processor will follow the normal rule for address translation in real-address mode (that
is, [CS base address = CS segment selector * 16]). To insure that the base address in the
CS register remains unchanged until the EPROM based software-initialization code is
completed, the code must not contain a far jump or far call or allow an interrupt to occur
(which would cause the CS selector value to be changed).
[CS base address = CS segment selector * 16]
F000H * 16 = F0000H
^^^^^^ (it's not 0xFFFF0000)
==> "CS base address" is not "base address in CS register" ?
BOOK: ISA system architecture
IP + FFF0h
FFFF0h = physical memory address
==> Why the reset mem addresses are different? Which one is correct?
1. which point does the BIOS start from? reset_vector? transition32? entry_elf?
2. If I only compile seabios, and load the bios.bin to qemu, coreboot will not be used?
what's the relationship between coreboot and seabios ?