Re: [SeaBIOS] Updating SeaBIOS on a Chromebook (Was: [PATCH] ps2: disable the keyboard and mouse before flushing the queue)

[Anthony Liguori]

Thanks Stefan!

I'll give it a try this evening.

Regards,

Anthony Liguori

Stefan Reinauer <[e-mail]> writes:
> Hi Anthony,
>
> In order to build a working SeaBIOS for the Pixel, you should use our
> ChromeOS tree because unfortunately we have not been able to upstream all
> the patches we carry around yet.
>
> $ git clone
> https://gerrit.chromium.org/gerrit/p/chromiumos/third_party/seabios.git
> $ cd seabios
> $ git checkout origin/chromeos-2012.05.12
>
> Build it with:
> $ cp default.config .config
> $ make
>
> Then create a CBFS
>
> # get the PCI option rom
> $ wget http://www.coreboot.org/~stepan/pci8086,0166.rom
> # Create a dummy bootblock to make cbfstool happy
> $ dd if=/dev/zero of=bootblock count=1 bs=64
> # Create empty CBFS
> $ cbfstool seabios.cbfs create -s $(( 2*1024*1024 )) -B bootblock -m x86
> # Add SeaBIOS binary to CBFS
> $ cbfstool seabios.cbfs add-payload -f out/bios.bin.elf -n payload -c lzma
> # Add VGA option rom to CBFS
> $ cbfstool seabios.cbfs add -f pci8086,0166.rom -n pci8086,0166.rom -t
> optionrom
> # Add additional configuration
> $ cbfstool seabios.cbfs add -f bootorder -n bootorder -t raw
> $ cbfstool seabios.cbfs add -f boot-menu-wait -n boot-menu-wait -t raw
> # Print CBFS inventory
> $ cbfstool seabios.cbfs print
> # Fix up CBFS to live at 0xffc00000. The last four bytes of a CBFS
> # image are a pointer to the CBFS master header. Per default a CBFS
> # lives at 4G - rom size, and the CBFS master header ends up at
> # 0xffffffa0. However our CBFS lives at 4G-4M and is 2M in size, so
> # the CBFS master header is at 0xffdfffa0 instead. The two lines
> # below correct the according byte in that pointer to make all CBFS
> # parsing code happy. In the long run we should fix cbfstool and
> # remove this workaround.
> /bin/echo -ne \\0737 | dd of=seabios.cbfs seek=$(( (2*1024*1024) - 2 ))
> bs=1 conv=notrunc
>
> That's it. :-)
>
> I also uploaded an image with your change to
>
> http://www.coreboot.org/~stepan/seabios.cbfs.bz2
>
> Flash it on the ChromeBook with:
>
> # cd /tmp
> # flashrom -r image.rom
> # dd if=seabios.cbfs of=image.rom seek=2 bs=2M conv=notrunc
> # flashrom -w image.rom -i RW_LEGACY
>
> On Thu, Apr 25, 2013 at 9:15 AM, ron minnich <[e-mail]> wrote:
> > stefan, how do we fix this?
> >
> > On Wed, Apr 24, 2013 at 6:36 PM, Anthony Liguori <[e-mail]>
> > wrote:
> > > Hi Ron,
> > >
> > > I just got a lovely new Pixel and noticed the following problem with
> > > SeaBIOS.  Any chance you know how I can update the SeaBIOS firmware to
> > > test this?  Or perhaps the person to poke to get fixes included in the
> > > shipped SeaBIOS?
> > >
> > > Regards,
> > >
> > > Anthony Liguori
> > >
> > > ---------- Forwarded message ----------
> > > From: "Anthony Liguori" <[e-mail]>
> > > To: "" <[e-mail]>
> > > Cc: "Kevin O'Connor" <[e-mail]> , "Anthony Liguori" <
> >
> > [e-mail]>
> > > Date: Wed, 24 Apr 2013 20:32:09 -0500
> > > Subject: [PATCH] ps2: disable the keyboard and mouse before flushing the
> > > queue
> > > If SeaBIOS is run as a payload via coreboot (and presumably as a
> > > CSM), then it's possible the keyboard or mouse will still be
> > > enabled.  This can lead to data being queued even after the flush
> > > function attempts to clear the queue.
> > >
> > > Disabling the keyboard/mouse prior to flushing is pretty standard
> > > in DOS programming so it's not surprising that it's needed here.
> > >
> > > I believe this problem manifests with the Chromebook Pixel.  People
> > > have reported that sometimes the 'ESC to Select Boot Devices'
> > > doesn't work.  I can reproduce this faithfully by holding 'Ctrl-L'
> > > in the firmware screen during SeaBIOS initialization.
> > >
> > > I can't test this fix on an actual Pixel because I don't know how
> > > to update SeaBIOS but I have tested the patch under QEMU.
> > >
> > > Signed-off-by: Anthony Liguori <[e-mail]>
> > > ---
> > >  src/ps2port.c | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > >
> > > diff --git a/src/ps2port.c b/src/ps2port.c
> > > index 9b760fd..2169171 100644
> > > --- a/src/ps2port.c
> > > +++ b/src/ps2port.c
> > > @@ -55,6 +55,12 @@ static int
> > >  i8042_flush(void)
> > >  {
> > >      dprintf(7, "i8042_flush\n");
> > > +
> > > +    /* Disable the keyboard and mouse to prevent additional data from
> > > +     * being queued. */
> > > +    outb(0xad, PORT_PS2_STATUS);
> > > +    outb(0xa7, PORT_PS2_STATUS);
> > > +
> > >      int i;
> > >      for (i=0; i<I8042_BUFFER_SIZE; i++) {
> > >          u8 status = inb(PORT_PS2_STATUS);
> > > --
> > > 1.8.0