This series enables seabios to run on some Baytrail CPU based chromebooks. At least some of these machines do not support routing of legacy interrupts and at least some have SDHCI controllers that do not appear as regular PCI devices. This series is mainly a hack to get some minimal support on the hardware.
This series is also available at: https://github.com/KevinOConnor/seabios/tree/baytrail-testing
-Kevin
Kevin O'Connor (3): Add minimal support for machines without hardware interrupts ps2: Eliminate "etc/ps2-poll-only"; use CONFIG_HARDWARE_IRQ instead sdcard: Allow sdcard addresses to be specified in CBFS files
docs/Runtime_config.md | 2 +- src/Kconfig | 13 ++++++++++++- src/clock.c | 31 +++++++++++++++++++++++++------ src/hw/pic.c | 14 ++++++++++++++ src/hw/pic.h | 4 ++++ src/hw/ps2port.c | 16 ++++++---------- src/hw/sdcard.c | 48 ++++++++++++++++++++++++++++++++++++------------ src/hw/timer.c | 2 ++ src/stacks.c | 5 ++++- src/util.h | 1 + 10 files changed, 105 insertions(+), 31 deletions(-)
Some Chromebooks (with Baytrail CPUs) apparently do not support routing of legacy interrupts. This patch adds minimal support for running SeaBIOS in such an environment. Even with this patch, it is known that old operating systems and even some recent bootloaders will not function without real hardware interrupts.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/Kconfig | 13 ++++++++++++- src/clock.c | 31 +++++++++++++++++++++++++------ src/hw/pic.c | 14 ++++++++++++++ src/hw/pic.h | 4 ++++ src/hw/timer.c | 2 ++ src/stacks.c | 5 ++++- src/util.h | 1 + 7 files changed, 62 insertions(+), 8 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index 56a1b2f..b873cd3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -209,7 +209,7 @@ menu "Hardware support" help Support boot from LSI MegaRAID SAS scsi storage. config FLOPPY - depends on DRIVES + depends on DRIVES && HARDWARE_IRQ bool "Floppy controller" default y help @@ -301,6 +301,7 @@ menu "Hardware support" Support parallel ports. This also enables int 17 parallel port calls. config RTC_TIMER bool "Real Time Clock (RTC) scheduling" + depends on HARDWARE_IRQ default y help Support MC146818 Real Time Clock chip timer @@ -309,6 +310,16 @@ menu "Hardware support" Disabling this support does not disable access to the RTC cmos registers.
+ config HARDWARE_IRQ + bool "Hardware interrupts" + default y + help + Program and support hardware interrupts using the i8259 + programmable interrupt controller (PIC). This option must + be enabled in order to support most boot loaders. Only + disable this option if running on peculiar hardware known + not to support irq routing. + config USE_SMM depends on QEMU bool "System Management Mode (SMM)" diff --git a/src/clock.c b/src/clock.c index 2bb5209..c73545b 100644 --- a/src/clock.c +++ b/src/clock.c @@ -279,13 +279,10 @@ handle_1a(struct bregs *regs) } }
-// INT 08h System Timer ISR Entry Point -void VISIBLE16 -handle_08(void) +// Update main tick counter +static void +clock_update(void) { - debug_isr(DEBUG_ISR_08); - - // Update counter u32 counter = GET_BDA(timer_counter); counter++; // compare to one days worth of timer ticks at 18.2 hz @@ -300,6 +297,14 @@ handle_08(void) floppy_tick(); usb_check_event(); ps2_check_event(); +} + +// INT 08h System Timer ISR Entry Point +void VISIBLE16 +handle_08(void) +{ + debug_isr(DEBUG_ISR_08); + clock_update();
// chain to user timer tick INT #0x1c struct bregs br; @@ -310,6 +315,20 @@ handle_08(void) pic_eoi1(); }
+u32 last_timer_check VARLOW; + +// Simulate timer irq on machines without hardware irqs +void +clock_poll_irq(void) +{ + if (CONFIG_HARDWARE_IRQ) + return; + if (!timer_check(GET_LOW(last_timer_check))) + return; + SET_LOW(last_timer_check, timer_calc(ticks_to_ms(1))); + clock_update(); +} +
/**************************************************************** * IRQ based timer diff --git a/src/hw/pic.c b/src/hw/pic.c index 6ff6967..d8b9764 100644 --- a/src/hw/pic.c +++ b/src/hw/pic.c @@ -13,12 +13,16 @@ u16 pic_irqmask_read(void) { + if (!CONFIG_HARDWARE_IRQ) + return 0; return inb(PORT_PIC1_DATA) | (inb(PORT_PIC2_DATA) << 8); }
void pic_irqmask_write(u16 mask) { + if (!CONFIG_HARDWARE_IRQ) + return; outb(mask, PORT_PIC1_DATA); outb(mask >> 8, PORT_PIC2_DATA); } @@ -26,6 +30,8 @@ pic_irqmask_write(u16 mask) void pic_irqmask_mask(u16 off, u16 on) { + if (!CONFIG_HARDWARE_IRQ) + return; u8 pic1off = off, pic1on = on, pic2off = off>>8, pic2on = on>>8; outb((inb(PORT_PIC1_DATA) & ~pic1off) | pic1on, PORT_PIC1_DATA); outb((inb(PORT_PIC2_DATA) & ~pic2off) | pic2on, PORT_PIC2_DATA); @@ -34,6 +40,8 @@ pic_irqmask_mask(u16 off, u16 on) void pic_reset(u8 irq0, u8 irq8) { + if (!CONFIG_HARDWARE_IRQ) + return; // Send ICW1 (select OCW1 + will send ICW4) outb(0x11, PORT_PIC1_CMD); outb(0x11, PORT_PIC2_CMD); @@ -60,6 +68,8 @@ pic_setup(void) void enable_hwirq(int hwirq, struct segoff_s func) { + if (!CONFIG_HARDWARE_IRQ) + return; pic_irqmask_mask(1 << hwirq, 0); int vector; if (hwirq < 8) @@ -72,6 +82,8 @@ enable_hwirq(int hwirq, struct segoff_s func) static u8 pic_isr1_read(void) { + if (!CONFIG_HARDWARE_IRQ) + return 0; // 0x0b == select OCW1 + read ISR outb(0x0b, PORT_PIC1_CMD); return inb(PORT_PIC1_CMD); @@ -80,6 +92,8 @@ pic_isr1_read(void) static u8 pic_isr2_read(void) { + if (!CONFIG_HARDWARE_IRQ) + return 0; // 0x0b == select OCW1 + read ISR outb(0x0b, PORT_PIC2_CMD); return inb(PORT_PIC2_CMD); diff --git a/src/hw/pic.h b/src/hw/pic.h index 6947b6e..f2d9f61 100644 --- a/src/hw/pic.h +++ b/src/hw/pic.h @@ -34,6 +34,8 @@ static inline void pic_eoi1(void) { + if (!CONFIG_HARDWARE_IRQ) + return; // Send eoi (select OCW2 + eoi) outb(0x20, PORT_PIC1_CMD); } @@ -41,6 +43,8 @@ pic_eoi1(void) static inline void pic_eoi2(void) { + if (!CONFIG_HARDWARE_IRQ) + return; // Send eoi (select OCW2 + eoi) outb(0x20, PORT_PIC2_CMD); pic_eoi1(); diff --git a/src/hw/timer.c b/src/hw/timer.c index 882b772..03d22b2 100644 --- a/src/hw/timer.c +++ b/src/hw/timer.c @@ -242,6 +242,8 @@ ticks_from_ms(u32 ms) void pit_setup(void) { + if (!CONFIG_HARDWARE_IRQ) + return; // timer0: binary count, 16bit count, mode 2 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE); // maximum count of 0000H = 18.2Hz diff --git a/src/stacks.c b/src/stacks.c index e67aeb6..7759c57 100644 --- a/src/stacks.c +++ b/src/stacks.c @@ -671,6 +671,8 @@ check_irqs(void) stack_hop_back(0, 0, _cfunc16_check_irqs); return; } + if (MODE16) + clock_poll_irq(); asm volatile("sti ; nop ; rep ; nop ; cli ; cld" : : :"memory"); }
@@ -706,7 +708,8 @@ wait_irq(void) void yield_toirq(void) { - if (!MODESEGMENT && (have_threads() || !CanInterrupt)) { + if (!CONFIG_HARDWARE_IRQ + || (!MODESEGMENT && (have_threads() || !CanInterrupt))) { // Threads still active or irqs not available - do a yield instead. yield(); return; diff --git a/src/util.h b/src/util.h index 8ea0ba0..327abeb 100644 --- a/src/util.h +++ b/src/util.h @@ -53,6 +53,7 @@ int cdrom_boot(struct drive_s *drive_g); // clock.c void clock_setup(void); void handle_1583(struct bregs *regs); +void clock_poll_irq(void); u32 irqtimer_calc_ticks(u32 count); u32 irqtimer_calc(u32 msecs); int irqtimer_check(u32 end);
The "etc/ps2-poll-only" runtime setting is directly tied to the new CONFIG_HARDWARE_IRQ setting - use the compile time setting to control both.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- docs/Runtime_config.md | 1 - src/hw/ps2port.c | 16 ++++++---------- 2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 962a8a9..4ac0eae 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -180,7 +180,6 @@ There are several additional configuration options available in the | boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found | extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. | ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. -| ps2-poll-only | SeaBIOS normally sets up the PS2 port to generate interrupts on keyboard and mouse events. One may set this field to a non-zero value to have SeaBIOS periodically poll the PS2 port for events instead. This may be useful on machines that do not properly route PS2 port interrupts. | optionroms-checksum | Option ROMs are required to have correct checksums. However, some option ROMs in the wild don't correctly follow the specifications and have bad checksums. Set this to a zero value to allow SeaBIOS to execute them anyways. | pci-optionrom-exec | Controls option ROM execution for roms found on PCI devices (as opposed to roms found in CBFS/fw_cfg). Valid values are 0: Execute no ROMs, 1: Execute only VGA ROMs, 2: Execute all ROMs. The default is 2 (execute all ROMs). | s3-resume-vga-init | Set this to a non-zero value to instruct SeaBIOS to run the vga rom on an S3 resume. diff --git a/src/hw/ps2port.c b/src/hw/ps2port.c index c368afc..d5504f7 100644 --- a/src/hw/ps2port.c +++ b/src/hw/ps2port.c @@ -211,7 +211,6 @@ ps2_sendbyte(int aux, u8 command, int timeout) }
u8 Ps2ctr VARLOW = I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; -u8 Ps2poll VARFSEG;
static int __ps2_command(int aux, int command, u8 *param) @@ -345,10 +344,9 @@ ps2_mouse_command(int command, u8 *param)
// Update ps2ctr for mouse enable/disable. if (command == PSMOUSE_CMD_ENABLE || command == PSMOUSE_CMD_DISABLE) { - u8 ps2poll = GET_GLOBAL(Ps2poll); u8 ps2ctr = GET_LOW(Ps2ctr); if (command == PSMOUSE_CMD_ENABLE) - ps2ctr = ((ps2ctr | (ps2poll ? 0 : I8042_CTR_AUXINT)) + ps2ctr = ((ps2ctr | (CONFIG_HARDWARE_IRQ ? I8042_CTR_AUXINT : 0)) & ~I8042_CTR_AUXDIS); else ps2ctr = (ps2ctr | I8042_CTR_AUXDIS) & ~I8042_CTR_AUXINT; @@ -420,10 +418,11 @@ done: pic_eoi1(); }
+// Check for ps2 activity on machines without hardware irqs void ps2_check_event(void) { - if (! CONFIG_PS2PORT || !GET_GLOBAL(Ps2poll)) + if (! CONFIG_PS2PORT || CONFIG_HARDWARE_IRQ) return; u8 ps2ctr = GET_LOW(Ps2ctr); if ((ps2ctr & (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS)) @@ -510,7 +509,7 @@ ps2_keyboard_setup(void *data)
// Keyboard Mode: disable mouse, scan code convert, enable kbd IRQ Ps2ctr = (I8042_CTR_AUXDIS | I8042_CTR_XLATE - | (Ps2poll ? 0 : I8042_CTR_KBDINT)); + | (CONFIG_HARDWARE_IRQ ? I8042_CTR_KBDINT : 0));
/* Enable keyboard */ ret = ps2_kbd_command(ATKBD_CMD_ENABLE, NULL); @@ -528,11 +527,8 @@ ps2port_setup(void) return; dprintf(3, "init ps2port\n");
- Ps2poll = romfile_loadint("etc/ps2-poll-only", 0); - if (!Ps2poll) { - enable_hwirq(1, FUNC16(entry_09)); - enable_hwirq(12, FUNC16(entry_74)); - } + enable_hwirq(1, FUNC16(entry_09)); + enable_hwirq(12, FUNC16(entry_74));
run_thread(ps2_keyboard_setup, NULL); }
Allow a hardcoded address to be specified in cbfs files with a prefix of "etc/sdcard". Some real-world devices have valid SDHCI controllers that do not show up as PCI devices.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- docs/Runtime_config.md | 1 + src/hw/sdcard.c | 48 ++++++++++++++++++++++++++++++++++++------------ 2 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 4ac0eae..d6fea28 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -188,3 +188,4 @@ There are several additional configuration options available in the | floppy0 | Set this to the type of the first floppy drive in the system (only type 4 for 3.5 inch drives is supported). | floppy1 | The type of the second floppy drive in the system. See the description of **floppy0** for more info. | threads | By default, SeaBIOS will parallelize hardware initialization during bootup to reduce boot time. Multiple hardware devices can be initialized in parallel between vga initialization and option rom initialization. One can set this file to a value of zero to force hardware initialization to run serially. Alternatively, one can set this file to 2 to enable early hardware initialization that runs in parallel with vga, option rom initialization, and the boot menu. +| sdcard* | One may create one or more files with an "sdcard" prefix (eg, "etc/sdcard0") with the physical memory address of an SDHCI controller (one memory address per file). This may be useful for SDHCI controllers that do not appear as PCI devices, but are mapped to a consistent memory address. diff --git a/src/hw/sdcard.c b/src/hw/sdcard.c index 540e97c..8e7e954 100644 --- a/src/hw/sdcard.c +++ b/src/hw/sdcard.c @@ -10,6 +10,7 @@ #include "pci.h" // pci_config_readl #include "pci_ids.h" // PCI_CLASS_SYSTEM_SDHCI #include "pci_regs.h" // PCI_BASE_ADDRESS_0 +#include "romfile.h" // romfile_findprefix #include "stacks.h" // wait_preempt #include "std/disk.h" // DISK_RET_SUCCESS #include "string.h" // memset @@ -416,15 +417,8 @@ sdcard_set_frequency(struct sdhci_s *regs, u32 khz)
// Setup and configure an SD card controller static void -sdcard_controller_setup(void *data) +sdcard_controller_setup(struct sdhci_s *regs, int prio) { - struct pci_device *pci = data; - u16 bdf = pci->bdf; - wait_preempt(); // Avoid pci_config_readl when preempting - struct sdhci_s *regs = (void*)pci_config_readl(bdf, PCI_BASE_ADDRESS_0); - pci_config_maskw(bdf, PCI_COMMAND, 0, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - // Initialize controller u32 present_state = readl(®s->present_state); if (!(present_state & SP_CARD_INSERTED)) @@ -470,27 +464,57 @@ sdcard_controller_setup(void *data) drive->regs = regs; drive->card_type = card_type;
- dprintf(1, "Found SD Card at %02x:%02x.%x\n" - , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)); + dprintf(1, "Found SD Card at %p\n", regs); char *desc = znprintf(MAXDESCSIZE, "SD Card"); // XXX - boot_add_hd(&drive->drive, desc, bootprio_find_pci_device(pci)); + boot_add_hd(&drive->drive, desc, prio); return; fail: writeb(®s->power_control, 0); writew(®s->clock_control, 0); }
+static void +sdcard_pci_setup(void *data) +{ + struct pci_device *pci = data; + wait_preempt(); // Avoid pci_config_readl when preempting + // XXX - bars dependent on slot index register in pci config space + u32 regs = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0); + pci_config_maskw(pci->bdf, PCI_COMMAND, 0, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + int prio = bootprio_find_pci_device(pci); + sdcard_controller_setup((void*)regs, prio); +} + +static void +sdcard_romfile_setup(void *data) +{ + struct romfile_s *file = data; + int prio = bootprio_find_named_rom(file->name, 0); + u32 addr = romfile_loadint(file->name, 0); + dprintf(1, "Starting sdcard controller check at addr %x\n", addr); + sdcard_controller_setup((void*)addr, prio); +} + void sdcard_setup(void) { if (!CONFIG_SDCARD) return;
+ struct romfile_s *file = NULL; + for (;;) { + file = romfile_findprefix("etc/sdcard", file); + if (!file) + break; + run_thread(sdcard_romfile_setup, file); + } + struct pci_device *pci; foreachpci(pci) { if (pci->class != PCI_CLASS_SYSTEM_SDHCI || pci->prog_if >= 2) // Not an SDHCI controller following SDHCI spec continue; - run_thread(sdcard_controller_setup, pci); + run_thread(sdcard_pci_setup, pci); } }
On Mon, Aug 17, 2015 at 01:21:54PM -0400, Kevin O'Connor wrote:
This series enables seabios to run on some Baytrail CPU based chromebooks. At least some of these machines do not support routing of legacy interrupts and at least some have SDHCI controllers that do not appear as regular PCI devices. This series is mainly a hack to get some minimal support on the hardware.
This series is also available at: https://github.com/KevinOConnor/seabios/tree/baytrail-testing
FYI, I committed this series (along with the RTC patch).
-Kevin
On 2015-08-24 16:08, Kevin O'Connor wrote:
On Mon, Aug 17, 2015 at 01:21:54PM -0400, Kevin O'Connor wrote:
This series enables seabios to run on some Baytrail CPU based chromebooks. At least some of these machines do not support routing of legacy interrupts and at least some have SDHCI controllers that do not appear as regular PCI devices. This series is mainly a hack to get some minimal support on the hardware.
This series is also available at: https://github.com/KevinOConnor/seabios/tree/baytrail-testing
FYI, I committed this series (along with the RTC patch).
Just a heads up - I'm compiling master with the only changes being to Kconfig and it's being treated like a dirty build. See http://johnlewis.ie:8080/job/SeaBIOS/40/console for an example. I understand you want to get the commit reference to aid debugging, so let me know if you want me to run another build from Jenkins to test a fix.
Best,
John.
John Lewis wrote:
Just a heads up - I'm compiling master with the only changes being to Kconfig
What changes do you have exactly?
and it's being treated like a dirty build.
How is it being marked as dirty?
Since you are essentially creating releases using a known environment I would encourage you to use the latest build-time VERSION flag (sorry, it changed so many times that I don't know what the current one is) to give it a clean identifier that makes sense to you and to your users.
//Peter
On Tue, Nov 03, 2015 at 10:30:23AM +0000, John Lewis wrote:
On 2015-08-24 16:08, Kevin O'Connor wrote:
On Mon, Aug 17, 2015 at 01:21:54PM -0400, Kevin O'Connor wrote:
This series enables seabios to run on some Baytrail CPU based chromebooks. At least some of these machines do not support routing of legacy interrupts and at least some have SDHCI controllers that do not appear as regular PCI devices. This series is mainly a hack to get some minimal support on the hardware.
This series is also available at: https://github.com/KevinOConnor/seabios/tree/baytrail-testing
FYI, I committed this series (along with the RTC patch).
Just a heads up - I'm compiling master with the only changes being to Kconfig and it's being treated like a dirty build. See http://johnlewis.ie:8080/job/SeaBIOS/40/console for an example. I understand you want to get the commit reference to aid debugging, so let me know if you want me to run another build from Jenkins to test a fix.
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
Thanks, -Kevin
On 2015-11-03 13:02, Kevin O'Connor wrote:
On Tue, Nov 03, 2015 at 10:30:23AM +0000, John Lewis wrote:
On 2015-08-24 16:08, Kevin O'Connor wrote:
On Mon, Aug 17, 2015 at 01:21:54PM -0400, Kevin O'Connor wrote:
This series enables seabios to run on some Baytrail CPU based chromebooks. At least some of these machines do not support routing of legacy interrupts and at least some have SDHCI controllers that do not appear as regular PCI devices. This series is mainly a hack to get some minimal support on the hardware.
This series is also available at: https://github.com/KevinOConnor/seabios/tree/baytrail-testing
FYI, I committed this series (along with the RTC patch).
Just a heads up - I'm compiling master with the only changes being to Kconfig and it's being treated like a dirty build. See http://johnlewis.ie:8080/job/SeaBIOS/40/console for an example. I understand you want to get the commit reference to aid debugging, so let me know if you want me to run another build from Jenkins to test a fix.
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
Thanks,
John.
On Tue, Nov 03, 2015 at 01:09:39PM +0000, John Lewis wrote:
On 2015-11-03 13:02, Kevin O'Connor wrote:
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
What does the build output with the patch below?
-Kevin
--- a/scripts/buildversion.py +++ b/scripts/buildversion.py @@ -14,6 +14,8 @@ VERSION_FORMAT = """
# Obtain version info from "git" program def git_version(): + sys.stdout.write("CWD=%s PATH=%s FILES=%s\n" % ( + os.getcwd(), os.environ['PATH'], os.listdir(os.getcwd()))) if not os.path.exists('.git'): return "" params = "git describe --tags --long --dirty".split()
On 2015-11-03 13:23, Kevin O'Connor wrote:
On Tue, Nov 03, 2015 at 01:09:39PM +0000, John Lewis wrote:
On 2015-11-03 13:02, Kevin O'Connor wrote:
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
What does the build output with the patch below?
CWD=/var/lib/jenkins/jobs/SeaBIOS/workspace PATH=/sbin:/usr/sbin:/bin:/usr/bin FILES=['docs', 'vgasrc', 'COPYING.LESSER', 'scripts', 'README', 'COPYING', '.config', 'Makefile', 'src', 'out', '.gitignore', '.git', '.config.old', 'buildversion.patch']
John.
On Sun, Nov 08, 2015 at 11:44:26AM +0000, John Lewis wrote:
On 2015-11-03 13:23, Kevin O'Connor wrote:
On Tue, Nov 03, 2015 at 01:09:39PM +0000, John Lewis wrote:
On 2015-11-03 13:02, Kevin O'Connor wrote:
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
What does the build output with the patch below?
CWD=/var/lib/jenkins/jobs/SeaBIOS/workspace PATH=/sbin:/usr/sbin:/bin:/usr/bin FILES=['docs', 'vgasrc', 'COPYING.LESSER', 'scripts', 'README', 'COPYING', '.config', 'Makefile', 'src', 'out', '.gitignore', '.git', '.config.old', 'buildversion.patch']
Odd. Can you report the output with the patch below instead?
-Kevin
--- a/scripts/buildversion.py +++ b/scripts/buildversion.py @@ -14,13 +14,19 @@ VERSION_FORMAT = """
# Obtain version info from "git" program def git_version(): + sys.stdout.write("CWD=%s PATH=%s FILES=%s\n" % ( + os.getcwd(), os.environ['PATH'], os.listdir(os.getcwd()))) if not os.path.exists('.git'): return "" params = "git describe --tags --long --dirty".split() + sys.stdout.write("try git %s\n" % (params,)) try: ver = subprocess.check_output(params).decode().strip() except: + import traceback + sys.stdout.write("git exc: %s\n" % (traceback.format_exc(),)) return "" + sys.stdout.write("git ver %s\n" % (ver,)) return ver
# Look for version in a ".version" file. Official release tarballs
On 2015-11-08 13:24, Kevin O'Connor wrote:
On Sun, Nov 08, 2015 at 11:44:26AM +0000, John Lewis wrote:
On 2015-11-03 13:23, Kevin O'Connor wrote:
On Tue, Nov 03, 2015 at 01:09:39PM +0000, John Lewis wrote:
On 2015-11-03 13:02, Kevin O'Connor wrote:
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
What does the build output with the patch below?
CWD=/var/lib/jenkins/jobs/SeaBIOS/workspace PATH=/sbin:/usr/sbin:/bin:/usr/bin FILES=['docs', 'vgasrc', 'COPYING.LESSER', 'scripts', 'README', 'COPYING', '.config', 'Makefile', 'src', 'out', '.gitignore', '.git', '.config.old', 'buildversion.patch']
Odd. Can you report the output with the patch below instead?
CWD=/var/lib/jenkins/jobs/SeaBIOS/workspace PATH=/sbin:/usr/sbin:/bin:/usr/bin FILES=['docs', 'vgasrc', 'COPYING.LESSER', 'scripts', 'README', 'COPYING', '.config', 'Makefile', 'src', 'out', '.gitignore', '.git', '.config.old'] try git ['git', 'describe', '--tags', '--long', '--dirty'] git exc: Traceback (most recent call last): File "./scripts/buildversion.py", line 24, in git_version ver = subprocess.check_output(params).decode().strip() AttributeError: 'module' object has no attribute 'check_output'
John.
On 2015-11-08 13:24, Kevin O'Connor wrote:
On Sun, Nov 08, 2015 at 11:44:26AM +0000, John Lewis wrote:
On 2015-11-03 13:23, Kevin O'Connor wrote:
On Tue, Nov 03, 2015 at 01:09:39PM +0000, John Lewis wrote:
On 2015-11-03 13:02, Kevin O'Connor wrote:
That log shows that git wasn't found during the build. Is there something in Jenkins that prevents the build from accessing git or is git not in the path?
It's more or less a default Jenkins install, so Git mustn't be available inside the workspace. I'll see what I can do about that. I guess it's one to watch out for in future.
What does the build output with the patch below?
CWD=/var/lib/jenkins/jobs/SeaBIOS/workspace PATH=/sbin:/usr/sbin:/bin:/usr/bin FILES=['docs', 'vgasrc', 'COPYING.LESSER', 'scripts', 'README', 'COPYING', '.config', 'Makefile', 'src', 'out', '.gitignore', '.git', '.config.old', 'buildversion.patch']
Odd. Can you report the output with the patch below instead?
It seems the version of Python with CentOS 6.3 is too old.
On Sun, Nov 08, 2015 at 05:35:16PM +0000, John Lewis wrote:
On 2015-11-08 13:24, Kevin O'Connor wrote:
Odd. Can you report the output with the patch below instead?
It seems the version of Python with CentOS 6.3 is too old.
Okay - we'll have to work around that. What version of python does it have (python --version) ?
-Kevin
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John Lewis -
Kevin O'Connor -
Peter Stuge