[SeaBIOS] [Qemu-devel] [PATCH RFC 04/17] hw/acpi: add _CRS method for extra root busses

[Marcel Apfelbaum]

Save the IO/mem ranges assigned to the extra root busses
to be removed from the root bus 0 range.

Todo: find the actual bus numbers range for the root busses.

Signed-off-by: Marcel Apfelbaum 
---
 hw/i386/acpi-build.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index cb77fa3..740254a 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -719,6 +719,109 @@ static AcpiAml build_prt(void)
     return method;
  }

+typedef struct PciMemoryRangeEntry {
+    QLIST_ENTRY(PciMemoryRangeEntry) entry;
+    PciMemoryRange range;
+} PciMemoryRangeEntry;
+
+typedef QLIST_HEAD(PciMemoryRangeQ, PciMemoryRangeEntry) PciMemoryRangeQ;
+
+static void pci_mem_range_insert(PciMemoryRangeQ *list, PciMemoryRange range) {
+    PciMemoryRangeEntry *entry, *e;
+
+    if (!range.base) {
+        return;
+    }
+
+    if (QLIST_EMPTY(list)) {
+        e = g_malloc(sizeof(*entry));
+        e->range = range;
+        QLIST_INSERT_HEAD(list, e, entry);
+
+        return;
+    }
+
+    QLIST_FOREACH(entry, list, entry) {
+        if (entry->range.limit < range.base) {
+            continue;
+        }
+
+        e = g_malloc(sizeof(*entry));
+        e->range = range;
+        QLIST_INSERT_BEFORE(entry, e, entry);
+        break;
+    }
+}
+
+static void pci_mem_range_list_free(PciMemoryRangeQ *list)
+{
+    PciMemoryRangeEntry *entry, *next;
+
+    QLIST_FOREACH_SAFE(entry, list, entry, next) {
+        QLIST_REMOVE(entry, entry);
+        g_free(entry);
+    }
+}
+
+static AcpiAml build_crs(PcPciInfo *pci, PciInfo *bus_info,
+                         PciMemoryRangeQ *io_ranges,
+                         PciMemoryRangeQ *mem_ranges)
+{
+    PciDeviceInfoList *dev_list;
+    PciMemoryRange range;
+    AcpiAml crs;
+
+    crs = acpi_resource_template();
+    /* todo: find the actual bus number range */
+    aml_append(&crs,
+            acpi_word_bus_number(acpi_min_fixed, acpi_max_fixed, acpi_pos_decode,
+                0x0000, bus_info->bus, bus_info->bus + 1, 0x0000, 0x2));
+
+    for (dev_list = bus_info->devices; dev_list; dev_list = dev_list->next) {
+        PciBridgeInfo *bridge_info = dev_list->value->pci_bridge;
+        if (!dev_list->value->has_pci_bridge) {
+            continue;
+        }
+
+        aml_append(&crs,
+                acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+                    acpi_pos_decode, acpi_entire_range,
+                    0x0000,
+                    bridge_info->bus.io_range->base,
+                    bridge_info->bus.io_range->limit,
+                    0x0000,
+                    bridge_info->bus.io_range->limit -
+                    bridge_info->bus.io_range->base + 1));
+        range = *bridge_info->bus.io_range;
+        pci_mem_range_insert(io_ranges, range);
+
+        aml_append(&crs,
+                acpi_dword_memory(acpi_pos_decode, acpi_min_fixed,
+                    acpi_max_fixed, acpi_non_cacheable, acpi_ReadWrite,
+                    0,
+                    bridge_info->bus.memory_range->base,
+                    bridge_info->bus.memory_range->limit,
+                    0,
+                    bridge_info->bus.memory_range->limit -
+                    bridge_info->bus.memory_range->base + 1));
+        range = *bridge_info->bus.memory_range;
+        pci_mem_range_insert(mem_ranges, range);
+        aml_append(&crs,
+                acpi_dword_memory(acpi_pos_decode, acpi_min_fixed,
+                    acpi_max_fixed, acpi_non_cacheable, acpi_ReadWrite,
+                    0,
+                    bridge_info->bus.prefetchable_range->base,
+                    bridge_info->bus.prefetchable_range->limit,
+                    0,
+                    bridge_info->bus.prefetchable_range->limit -
+                    bridge_info->bus.prefetchable_range->base + 1));
+        range = *bridge_info->bus.prefetchable_range;
+        pci_mem_range_insert(mem_ranges, range);
+    }
+
+    return crs;
+}
+
 static void
 build_ssdt(AcpiAml *table_aml, GArray *linker,
            AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -729,6 +832,8 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
     unsigned acpi_cpus = guest_info->apic_id_limit;
     AcpiAml pkg, scope, dev, method, crs, field, ifctx, ssdt;
     int i;
+    PciMemoryRangeQ io_ranges = QLIST_HEAD_INITIALIZER(io_ranges);
+    PciMemoryRangeQ mem_ranges = QLIST_HEAD_INITIALIZER(mem_ranges);

/* The current AML generator can cover the APIC ID range [0..255],
      * inclusive, for VCPU hotplug. */
@@ -762,9 +867,14 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
             aml_append(&dev,
                 acpi_name_decl("_BBN", acpi_int((uint8_t)bus_info->bus)));
             aml_append(&dev, build_prt());
+            crs = build_crs(pci, bus_info, &io_ranges, &mem_ranges);
+            aml_append(&dev, acpi_name_decl("_CRS", crs));
             aml_append(&scope, dev);
             aml_append(&ssdt, scope);
         }
+
+        pci_mem_range_list_free(&io_ranges);
+        pci_mem_range_list_free(&mem_ranges);
         qapi_free_PciInfoList(info_list);
     }