1 - On boot, have SeaBIOS relocate all of it's 32bit code to permanent high ram.
I have done some experimental reloc code for Coreboot. I took it from memtest86. Check how to do that. The best would be to simply add diferent base to segs. You have the physmem accessors anyway so maybe way to go here. Check FILO. I think it uses this.
2 - Have the build separate out the POST code from other 32bit code (eg, boot& resume) and store the POST code in a separate CBFS/fw_cfg "file". During boot SeaBIOS would extract the separate POST code blob into temporary high ram and run it. Currently, the POST code is the bulk of the 32bit "flat" code (57K vs 10K).
CONS: It adds complexity during deployment as both the main SeaBIOS blob and the CBFS/fw_cfg POST blob would need to be copied.
And relocation perhaps necessary because during resume you would need to place it in some reserved range.
3 - On boot, relocate only POST code to temporary high ram, and have SeaBIOS reset the machine if the POST code is ever rerun.
CONS: Requires a reliable way of resetting the machine. CONS: SeaBIOS code is still limited to 256K size (c+d+e+f segments)Any thoughts? I kinda prefer option 3.
Yes looks good to me too (and easiest) How you deal with resume here?
Resetting the machine on a rerun of POST would be a good thing to do anyway, as trying to re-post the machine has never really worked well. It does, however, make the build a bit more complex.
Reseting the machine can be done in various ways:
http://lxr.linux.no/#linux+v2.6.35/arch/x86/kernel/reboot.c
What about other CPUs?
Thanks, Rudolf