Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/fw/smp.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/src/fw/smp.c b/src/fw/smp.c index 579acdb..711eb27 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -7,16 +7,18 @@
#include "config.h" // CONFIG_* #include "hw/rtc.h" // CMOS_BIOS_SMP_COUNT +#include "memmap.h" // ioremap #include "output.h" // dprintf #include "romfile.h" // romfile_loadint #include "stacks.h" // yield #include "util.h" // smp_setup #include "x86.h" // wrmsr
-#define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) -#define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0) -#define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350) -#define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360) +#define APIC_ICR_LOW 0x300 +#define APIC_SVR 0x0F0 +#define APIC_LINT0 0x350 +#define APIC_LINT1 0x360 +#define APIC_SIZE 0x400
#define APIC_ENABLED 0x0100
@@ -105,23 +107,24 @@ smp_setup(void) *(u64*)BUILD_AP_BOOT_ADDR = new;
// enable local APIC - u32 val = readl(APIC_SVR); - writel(APIC_SVR, val | APIC_ENABLED); + void *apic = ioremap(BUILD_APIC_ADDR, APIC_SIZE); + u32 val = readl(apic + APIC_SVR); + writel(apic + APIC_SVR, val | APIC_ENABLED);
/* Set LINT0 as Ext_INT, level triggered */ - writel(APIC_LINT0, 0x8700); + writel(apic + APIC_LINT0, 0x8700);
/* Set LINT1 as NMI, level triggered */ - writel(APIC_LINT1, 0x8400); + writel(apic + APIC_LINT1, 0x8400);
// Init the lock. writel(&SMPLock, 1);
// broadcast SIPI barrier(); - writel(APIC_ICR_LOW, 0x000C4500); + writel(apic + APIC_ICR_LOW, 0x000C4500); u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12; - writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); + writel(apic + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
// Wait for other CPUs to process the SIPI. u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1;