From d478ac82045a27f82f44ea9ce65f642197fe6078 Mon Sep 17 00:00:00 2001 From: David Woodhouse David.Woodhouse@intel.com Date: Fri, 25 Jan 2013 19:39:07 -0600 Subject: [PATCH] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update
Unless CONFIG_MALLOC_UPPERMEMORY is turned off, we expect to use the space between the top of option ROMs and the bottom of our own BIOS code as a stack. OVMF was previously marking the whole region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot method. Read-only stack considered harmful.
Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which allow the CSM to specify a memory region that needs to be writable, so provide that information.
Signed-off-by: David Woodhouse David.Woodhouse@intel.com --- With your incremental patch from 2013-12-02 at 12:46 -0500 merged.
However, this doesn't work if I have both CONFIG_MALLOC_UPPERMEMORY *and* CONFIG_EXTRA_STACK enabled. Symptoms are the same as the original problem which both CONFIG_MALLOC_UPPERMEMORY and the CSM spec update set out to solve: it works only with KVM enabled, because we're writing to regions which are supposed to be marked as ROM.
Last I see is:
handle_csm returning AX=0000 UmaAddress ef000, size 1000 InstallProtocolInterface: DB9A1E3D-45CB-4ABB-853B-E5387FDB2E2D 6950C30 tqemu: fatal: Trying to execute code outside RAM or ROM at 0x00000000000a0000
src/fw/csm.c | 9 +++++++++ src/std/LegacyBios.h | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+)
diff --git a/src/fw/csm.c b/src/fw/csm.c index a44ed26..1f85087 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -34,6 +34,10 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = { .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */, .OemIdStringPointer = (u32)"SeaBIOS", .AcpiRsdPtrPointer = (u32)&csm_rsdp, +#if CONFIG_MALLOC_UPPERMEMORY + .UmaAddress = (u32)&zonelow_base, + .UmaSize = 0x10000, +#endif };
EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table; @@ -49,6 +53,11 @@ csm_return(struct bregs *regs) dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
PICMask = pic_irqmask_read(); + if (CONFIG_MALLOC_UPPERMEMORY) { + u32 top = rom_get_max(); + csm_compat_table.UmaAddress = top; + csm_compat_table.UmaSize = (u32)zonelow_base + 0x10000 - top; + } __csm_return(regs); }
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h index cf0c3c5..5170c37 100644 --- a/src/std/LegacyBios.h +++ b/src/std/LegacyBios.h @@ -228,6 +228,26 @@ typedef struct { /// Maximum PCI bus number assigned. /// UINT8 LastPciBus; + + /// + /// Start address of UMB RAM + /// + UINT32 UmaAddress; + + /// + /// Size of UMB RAM + /// + UINT32 UmaSize; + + /// + /// Start address of persistent allocation in high (>1MiB) memory + /// + UINT32 HiPermanentMemoryAddress; + + /// + /// Size of persistent allocation in high (>1MiB) memory + /// + UINT32 HiPermanentMemorySize; } EFI_COMPATIBILITY16_TABLE;
///