Hi,
Well, the idea is to adapt to the world moving forward. Running a 64-bit capable OS is standard these days, and the resources needed by devices (especially GPUs) are becoming larger and larger.
Yes, there is the risk that (old) guests are unhappy with their PCI bars suddenly being mapped above 4G. Can happen only in case seabios handles pci initialization (i.e. when running on qemu, otherwise coreboot initializes the pci bars). I hope the memory check handles the 'old guest' case: when the guest can't handle addresses above 4G it is unlikely that qemu is configured to have memory mapped above 4G ...
does it break 32-bit PAE enabled guests (which can have more then 4Gb RAM configured)?
Well, depends on the guest OS I guess. Modern linux copes just fine, either uses PAE paging to access the PCI bars (seen with debian, works even in case the PCI bars are above the 64G limit of 32bit processors), or or it remaps the bars to places below 4G (seen with alpine which compiles i386 kernels with PAE=n).
take care, Gerd