On 08/08/13 10:22, Michael S. Tsirkin wrote:
On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd
32bit window is sized according to the installed memory.
logic is in seabios and you'll try to move it to qemu, using pci-info.
It wasn't in qemu before ...
The logic is in hw/i386/pc_piix.c and always was.
What exactly you are refering to?
pc_init1 which picks addresses and passes them on to
Yep. qemu figured where it wants map memory. The unused 32bit address
space goes into the pci hole. cmos memory size is set accordingly.
seabios gets the memory size from cmos, then it knows where the pci hole
starts. seabios rounds it up (i.e. may leave some of it unused) to be
able to cover the complete hole with a single mtrr entry, but that isn't
a issue and can be changed if needed. The mtrr thing is more or less
cosmetical anyway in a virtual machine.
configuration is in the cmos, firmware can figure where it can
place pci devices from that. There is no need for a new interface.
The assumption being that whatever is not memory is PCI?
I'm not sure that's right.
Maybe not in general, but I'm pretty sure for the x86 chipsets we are
emulating it is.
can initialize the hardware as it likes. For the most part
the OS can simply read the configuration from the pci config space.
Only for some hardware (Q35).
i440fx_init gets pci_hole_start and pci_hole_end.
This is in hardware (QEMU) and not configurable by firmware.
pci_hole_start == end of low memory (available via cmos).
pci_hole_end == 4G.
Another issue is where to start/end the 32 bit window
That's really a PV thing for QEMU, hardcoded at the moment in bios
Hmm? --verbose please. What issue to we have with the 32bit window?
I refer to PCI hole starting at 0xe0000000.
See above. It's not hardcoded in seabios. The upper limit for low
memory is hardcoded in qemu, i.e. large guests with 4G or more memory
get a hole starting at 0xe0000000. If you change that in qemu to be --
say -- 0xc0000000 instead seabios will handle it just fine.
You can see that today, just start a guest with 2G, 3G & 4G of memory,
then watch the pci hole size adapting in /proc/iomem.