On 01/26/2015 04:34 PM, Paul Menzel wrote:
Dear Timothy,
thank you for reporting this issue to the SeaBIOS mailing list.
Am Montag, den 26.01.2015, 12:57 -0600 schrieb Timothy Pearson:
I have a board here that uses an XGI Volari Z9s integrated graphics device. The board boots under coreboot and loads Linux, but if I add the appropriate VGA option ROM (extracted from the vendor BIOS) SeaBIOS hangs:
SeaBIOS (version rel-1.7.5-150-g301dd09-20150126_124858-apollo) Found mainboard ASUS KFSN4-DRE Relocating init from 0x000e6fe0 to 0x3ff95800 (size 42816) Found CBFS header at 0xfffffc80 CPU Mhz=2311 Found 26 PCI devices (max PCI bus is 05) Copying MPTABLE from 0x3ffe0400/3ffe0410 to 0x000f1550 Copying ACPI RSDP from 0x3ffe1400 to 0x000f1520 Copying SMBIOS entry point from 0x3ffec800 to 0x000f1500 Using pmtimer, ioport 0x2008 Scan for VGA option rom Running option rom at c000:0003
The Volari graphics initialise and work properly once Linux has booted and loaded the appropriate device drivers. For now I have been using SGABIOS for VGA emulation, however I would like to see the native VGA work on boot.
Is coreboot able to successfully run the Video BIOS? Just add it using the coreboot Kconfig menu.
Thanks,
Paul
No, coreboot hangs as well:
Root Device (ASUS KFSN4-DRE) CPU_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket F_1207) DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (NVIDIA CK804 Southbridge) PCI: 00:01.0 (NVIDIA CK804 Southbridge) PNP: 002e.0 (Winbond W83627THG Super I/O) PNP: 002e.1 (Winbond W83627THG Super I/O) PNP: 002e.2 (Winbond W83627THG Super I/O) PNP: 002e.3 (Winbond W83627THG Super I/O) PNP: 002e.5 (Winbond W83627THG Super I/O) PNP: 002e.7 (Winbond W83627THG Super I/O) PNP: 002e.8 (Winbond W83627THG Super I/O) PNP: 002e.9 (Winbond W83627THG Super I/O) PNP: 002e.a (Winbond W83627THG Super I/O) PNP: 002e.b (Winbond W83627THG Super I/O) PCI: 00:01.1 (NVIDIA CK804 Southbridge) I2C: 01:50 (unknown) I2C: 01:51 (unknown) I2C: 01:52 (unknown) I2C: 01:53 (unknown) I2C: 01:54 (unknown) I2C: 01:55 (unknown) I2C: 01:56 (unknown) I2C: 01:57 (unknown) PCI: 00:02.0 (NVIDIA CK804 Southbridge) PCI: 00:02.1 (NVIDIA CK804 Southbridge) PCI: 00:04.0 (NVIDIA CK804 Southbridge) PCI: 00:04.1 (NVIDIA CK804 Southbridge) PCI: 00:06.0 (NVIDIA CK804 Southbridge) PCI: 00:07.0 (NVIDIA CK804 Southbridge) PCI: 00:08.0 (NVIDIA CK804 Southbridge) PCI: 00:09.0 (NVIDIA CK804 Southbridge) PCI: 01:04.0 (NVIDIA CK804 Southbridge) PCI: 00:0a.0 (NVIDIA CK804 Southbridge) PCI: 00:0b.0 (NVIDIA CK804 Southbridge) PCI: 02:00.0 (NVIDIA CK804 Southbridge) PCI: 00:0c.0 (NVIDIA CK804 Southbridge) PCI: 03:00.0 (NVIDIA CK804 Southbridge) PCI: 00:0d.0 (NVIDIA CK804 Southbridge) PCI: 04:00.0 (NVIDIA CK804 Southbridge) PCI: 00:0e.0 (NVIDIA CK804 Southbridge) PCI: 00:0f.0 (NVIDIA CK804 Southbridge) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) PCI: 00:19.0 (AMD FAM10 Northbridge) PCI: 00:19.1 (AMD FAM10 Northbridge) PCI: 00:19.2 (AMD FAM10 Northbridge) PCI: 00:19.3 (AMD FAM10 Northbridge) PCI: 00:19.4 (AMD FAM10 Northbridge) APIC: 01 (unknown) APIC: 02 (unknown) APIC: 03 (unknown) APIC: 04 (unknown) APIC: 05 (unknown) APIC: 06 (unknown) APIC: 07 (unknown) SMBIOS tables: 333 bytes. POST: 0x9e POST: 0x9d Adding CBMEM entry as no. 5 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fdf Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0xdffed000 rom_table_end = 0xdffed000 ... aligned to 0xdfff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000dffdffff: RAM 3. 00000000dffe0000-00000000dfffffff: CONFIGURATION TABLES 4. 00000000e0000000-00000000efffffff: RESERVED 5. 0000000100000000-000000039fffffff: RAM Wrote coreboot table at: dffed000, 0x168 bytes, checksum 8058 coreboot table: 384 bytes. FREE SPACE 0. dfff5000 0000b000 GDT 1. dffe0200 00000200 SMP TABLE 2. dffe0400 00001000 ACPI 3. dffe1400 0000b400 SMBIOS 4. dffec800 00000800 COREBOOT 5. dffed000 00008000 POST: 0x7a CBFS: located payload @ fff253f8, 54870 bytes. Loading segment from rom address 0xfff253f8 code (compression=1) New segment dstaddr 0xe6398 memsize 0x19c68 srcaddr 0xfff25430 filesize 0xd61e Loading segment from rom address 0xfff25414 Entry Point 0x000fd4cc Bounce Buffer at dfdf3000, 2015328 bytes Loading Segment: addr: 0x00000000000e6398 memsz: 0x0000000000019c68 filesz: 0x000000000000d61e lb: [0x0000000000100000, 0x00000000001f6030) Post relocation: addr: 0x00000000000e6398 memsz: 0x0000000000019c68 filesz: 0x000000000000d61e using LZMA [ 0x000e6398, 00100000, 0x00100000) <- fff25430 dest 000e6398, end 00100000, bouncebuffer dfdf3000 Loaded segments POST: 0x7b Jumping to boot code at 000fd4cc POST: 0xf8 CPU0: stack: 00135000 - 00136000, lowest used address 00135a2c, stack used: 1492 bytes entry = 0x000fd4cc lb_start = 0x00100000 lb_size = 0x000f6030 buffer = 0xdfdf3000
As everything else works I probably won't spend much more time on this, but I am willing to test if anyone has ideas on how to fix the issue.
I take it coreboot cannot natively initialise XGI Volari devices?
Thanks!