Create memory buses and introduce function to adjust memory map for hotplug-able dimms.
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovitis@profitbricks.com --- hw/pc_q35.c | 1 + hw/q35.c | 27 +++++++++++++++++++++++++++ hw/q35.h | 5 +++++ 3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c index 3429a9a..e6375bf 100644 --- a/hw/pc_q35.c +++ b/hw/pc_q35.c @@ -41,6 +41,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "fw_cfg.h"
/* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 diff --git a/hw/q35.c b/hw/q35.c index efebc27..cc27d72 100644 --- a/hw/q35.c +++ b/hw/q35.c @@ -236,12 +236,39 @@ static void mch_reset(DeviceState *qdev) mch_update(mch); }
+static hwaddr mch_dimm_offset(DeviceState *dev, uint64_t size) +{ + MCHPCIState *d = MCH_PCI_DEVICE(dev); + hwaddr ret; + + /* if dimm fits before pci hole, append it normally */ + if (d->below_4g_mem_size + size <= MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT) { + ret = d->below_4g_mem_size; + d->below_4g_mem_size += size; + } + /* otherwise place it above 4GB */ + else { + ret = 0x100000000LL + d->above_4g_mem_size; + d->above_4g_mem_size += size; + } + + return ret; +} + static int mch_init(PCIDevice *d) { int i; hwaddr pci_hole64_size; MCHPCIState *mch = MCH_PCI_DEVICE(d);
+ /* Initialize 2 GMC DRAM channels x 4 DRAM ranks each */ + mch->dram_channel[0] = dimm_bus_create(OBJECT(d), "membus.0", 4, + mch_dimm_offset); + mch->dram_channel[1] = dimm_bus_create(OBJECT(d), "membus.1", 4, + mch_dimm_offset); + /* Initialize paravirtual memory bus */ + mch->pv_dram_channel = dimm_bus_create(OBJECT(d), "membus.pv", 0, + mch_dimm_offset); /* setup pci memory regions */ memory_region_init_alias(&mch->pci_hole, "pci-hole", mch->pci_address_space, diff --git a/hw/q35.h b/hw/q35.h index e34f7c1..bf76dc8 100644 --- a/hw/q35.h +++ b/hw/q35.h @@ -34,6 +34,7 @@ #include "acpi.h" #include "acpi_ich9.h" #include "pam.h" +#include "dimm.h"
#define TYPE_Q35_HOST_DEVICE "q35-pcihost" #define Q35_HOST_DEVICE(obj) \ @@ -56,6 +57,10 @@ typedef struct MCHPCIState { uint8_t smm_enabled; ram_addr_t below_4g_mem_size; ram_addr_t above_4g_mem_size; + /* GMCH allows for 2 DRAM channels x 4 DRAM ranks each */ + DimmBus * dram_channel[2]; + /* paravirtual memory bus */ + DimmBus *pv_dram_channel; } MCHPCIState;
typedef struct Q35PCIHost {