[SeaBIOS] [rfc patch qemu 4/4] wakeup: uhci support

[Gerd Hoffmann]

Implement the (intel-specific) pci configuration register 0xc4, which is
a bitmask saying which ports are allowed to wakeup the system.

Also assign gpe bit 0x0b (used only in case uhci handles device 01.2).

Signed-off-by: Gerd Hoffmann 
---
 hw/usb/hcd-uhci.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index 8f652d2..b2da21d 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -32,6 +32,7 @@
 #include "iov.h"
 #include "dma.h"
 #include "trace.h"
+#include "sysemu.h"

//#define DEBUG
 //#define DEBUG_DUMP_DATA
@@ -129,6 +130,7 @@ struct UHCIState {
     uint32_t fl_base_addr; /* frame list base address */
     uint8_t sof_timing;
     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
+    uint8_t system_wakeup;
     int64_t expire_time;
     QEMUTimer *frame_timer;
     QEMUBH *bh;
@@ -665,6 +667,22 @@ static void uhci_wakeup(USBPort *port1)
     }
 }

+static void uhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
+{
+    USBPort *port1 = ep->dev->port;
+    UHCIState *s = port1->opaque;
+
+    if (!(s->system_wakeup & (1 << port1->index))) {
+        return;
+    }
+    if (s->dev.devfn == PCI_DEVFN(1, 2)) {
+        /* piix3/4 chipset uhci controller */
+        qemu_system_wakeup_request(QEMU_WAKEUP_REASON_GPE_b);
+    } else {
+        qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
+    }
+}
+
 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 {
     USBDevice *dev;
@@ -1181,6 +1199,7 @@ static USBPortOps uhci_port_ops = {
 };

static USBBusOps uhci_bus_ops = {
+    .wakeup_endpoint = uhci_wakeup_endpoint,
 };

static int usb_uhci_common_initfn(PCIDevice *dev)
@@ -1242,6 +1261,17 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
     return 0;
 }

+static void usb_uhci_intel_write_config(PCIDevice *dev, uint32_t addr,
+                                        uint32_t val, int len)
+{
+    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
+
+    pci_default_write_config(dev, addr, val, len);
+    if (addr == 0xc4) {
+        s->system_wakeup = val;
+    }
+}
+
 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
 {
     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
@@ -1279,6 +1309,7 @@ static void piix3_uhci_class_init(ObjectClass *klass, void *data)

k->init = usb_uhci_common_initfn;
     k->exit = usb_uhci_exit;
+    k->config_write = usb_uhci_intel_write_config;
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
     k->revision = 0x01;
@@ -1301,6 +1332,7 @@ static void piix4_uhci_class_init(ObjectClass *klass, void *data)

k->init = usb_uhci_common_initfn;
     k->exit = usb_uhci_exit;
+    k->config_write = usb_uhci_intel_write_config;
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
     k->revision = 0x01;
@@ -1344,6 +1376,7 @@ static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

k->init = usb_uhci_common_initfn;
+    k->config_write = usb_uhci_intel_write_config;
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
     k->revision = 0x03;
@@ -1365,6 +1398,7 @@ static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

k->init = usb_uhci_common_initfn;
+    k->config_write = usb_uhci_intel_write_config;
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
     k->revision = 0x03;
@@ -1386,6 +1420,7 @@ static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

k->init = usb_uhci_common_initfn;
+    k->config_write = usb_uhci_intel_write_config;
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
     k->revision = 0x03;