On Mon, June 1, 2015 8:48 pm, Paulo Alcantara wrote:
This interface provides some registers within a
32-byte range and can be
acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
It's commonly used as a watchdog timer to detect system lockups through
SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If
NO_REBOOT bit is not set in GCS (General Control and Status register),
the system will be resetted upon second timeout if TCO_RLD register
wasn't previously written to prevent timeout.
This patch adds support to TCO watchdog logic and few other features
like mapping NMIs to SMIs (NMI2SMI_EN bit), system intruder detection,
etc. are not implemented yet.
v1 -> v2:
* add migration support for TCO I/O device state
* wake up only when total time expired instead of every 0.6s
* some cleanup suggested by Paolo Bonzini
v2 -> v3:
* set SECOND_TO_STS and BOOT_STS bits in TCO2_STS instead
* improve handling of TCO_LOCK bit in TCO1_CNT register
Michael, ping? :-)
(looks like there's a lot of ICH9 changes since this patchset was sent, so
you want me to rebase it against master and resend, please let me know)
Paulo Alcantara, C.E.S.A.R
Speaking for myself only.