The way the size is reported by the BAR register by checking if the device decodes certain bits or not implies that the address must be naturally aligned, i.e. aligned to the size.
El vie, 14 abr 2023 17:38, Peter Stuge peter@stuge.se escribió:
Gerd Hoffmann wrote:
A 2G 32-bit bar simply can't be mapped anywhere on x86. It must be below 4G,
Agree..
and it must be 2G-aligned.
..but I can't find this requirement. Why do you say?
The one mention of alignment in PCI 3.0 is for the Expansion ROM BAR, where *the device* can indicate its required alignment.
So why couldn't a 2G BAR be mapped at 1G?
If must size-align after all then there is at minimum one creative solution achieved by dividing the one 2G BAR into two 1G BARs, that can then be mapped at 1G and 2G. This could probably be hidden from the rest of the device by the bus interface. Just be prepared that firmware can map the two BARs in any order!
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