[SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 27/28] apci: fix PXB behaviour if used with unsupported BIOS

[Marcel Apfelbaum]

PXB does not work with an unsupported BIOS, but should
not interfere with normal OS operation.

Fix this by not adding PXB mem/IO chunks to _CRS
if they weren't configured by BIOS.

Signed-off-by: Marcel Apfelbaum 
---
 hw/i386/acpi-build.c | 71 +++++++++++++++++++++++++++++++---------------------
 1 file changed, 42 insertions(+), 29 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2bc8a80..416972c 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -780,6 +780,10 @@ static Aml *build_crs(PcPciInfo *pci, PciInfo *bus_info,
             range_base = region->value->address;
             range_limit = region->value->address + region->value->size - 1;

+            if (range_base == PCI_BAR_UNMAPPED) {
+                continue;
+            }
+
             if (!strcmp(region->value->type, "io")) {
                 aml_append(crs,
                     aml_word_io(aml_min_fixed, aml_max_fixed,
@@ -813,41 +817,50 @@ static Aml *build_crs(PcPciInfo *pci, PciInfo *bus_info,

range_base = bridge_info->bus.io_range->base;
             range_limit = bridge_info->bus.io_range->limit;
-            aml_append(crs,
-                aml_word_io(aml_min_fixed, aml_max_fixed,
-                            aml_pos_decode, aml_entire_range,
-                            0,
-                            range_base,
-                            range_limit,
-                            0,
-                            range_limit - range_base + 1));
-            crs_range_insert(io_ranges, range_base, range_limit);
+            /* PCI Bridge I/O limit is aligned to 4K */
+            if (range_limit >> 12) {
+                aml_append(crs,
+                    aml_word_io(aml_min_fixed, aml_max_fixed,
+                                aml_pos_decode, aml_entire_range,
+                                0,
+                                range_base,
+                                range_limit,
+                                0,
+                                range_limit - range_base + 1));
+                crs_range_insert(io_ranges, range_base, range_limit);
+            }

range_base = bridge_info->bus.memory_range->base;
             range_limit = bridge_info->bus.memory_range->limit;
-             aml_append(crs,
-                aml_dword_memory(aml_pos_decode, aml_min_fixed,
-                                 aml_max_fixed, aml_non_cacheable,
-                                 aml_ReadWrite,
-                                 0,
-                                 range_base,
-                                 range_limit,
-                                 0,
-                                 range_limit - range_base + 1));
-            crs_range_insert(mem_ranges, range_base, range_limit);
+            /* PCI Bridge MEM limit is aligned to 1M */
+            if (range_limit >> 20) {
+                aml_append(crs,
+                    aml_dword_memory(aml_pos_decode, aml_min_fixed,
+                                     aml_max_fixed, aml_non_cacheable,
+                                     aml_ReadWrite,
+                                     0,
+                                     range_base,
+                                     range_limit,
+                                     0,
+                                     range_limit - range_base + 1));
+                    crs_range_insert(mem_ranges, range_base, range_limit);
+            }

range_base = bridge_info->bus.prefetchable_range->base;
             range_limit = bridge_info->bus.prefetchable_range->limit;
-            aml_append(crs,
-                aml_dword_memory(aml_pos_decode, aml_min_fixed,
-                                 aml_max_fixed, aml_non_cacheable,
-                                 aml_ReadWrite,
-                                 0,
-                                 range_base,
-                                 range_limit,
-                                 0,
-                                 range_limit - range_base + 1));
-            crs_range_insert(mem_ranges, range_base, range_limit);
+            /* PCI Bridge Prefetch MEM limit is aligned to 1M */
+            if (range_limit >> 20) {
+                aml_append(crs,
+                    aml_dword_memory(aml_pos_decode, aml_min_fixed,
+                                     aml_max_fixed, aml_non_cacheable,
+                                     aml_ReadWrite,
+                                     0,
+                                     range_base,
+                                     range_limit,
+                                     0,
+                                     range_limit - range_base + 1));
+                crs_range_insert(mem_ranges, range_base, range_limit);
+            }
         }
     }