29 Nov
2013
29 Nov
'13
7:09 p.m.
On Fri, 2013-11-29 at 12:44 -0500, Kevin O'Connor wrote:
That should be okay, but would it ever actually be mapped below 1Meg? Where would it be mapped to: 0xa0000-0xc0000?
Somewhere down there. Or 0xc0000 even. There's no video here.
BTW, how does this "Quark" support compare with the PCI Oxford serial code that Google has been maintaining? http://git.chromium.org/gitweb/?p=chromiumos/third_party/seabios.git;a=commi...
Hm, close.
Mine is mmio32 not mmio8. So IER is at 0x4 in the BAR, IIR at 0x8 etc. And I need to specify the PCI B/D/F because I really need to use the one at 0000:14:5 not the other port at 0000:14.1.
But those are easy enough to solve.
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dwmw2