On Thu, Oct 13, 2011 at 12:18:08AM +0700, Darmawan Salihun wrote:
On 10/11/11, Kevin O'Connor kevin@koconnor.net wrote:
I suggest getting serial debugging working, and post the full log.
The full log is in the attachment. Anyway, I observed that the PCI ROM that I'm working with always got it's 3rd byte set to zero prior to being executed. I've just found where it's being modified but have yet to find the corresponding code in the entire "debugging system"
SeaBIOS wont modify the rom. However, the rom might self-modify itself when it is run.
[...]
Real mode stub @00000600: 606 bytes Calling Option ROM... oprom: INT# 0x10
If you are using SeaBIOS, you should instruct coreboot to not execute option roms. Disable both CONFIG_VGA_ROM_RUN and CONFIG_PCI_ROM_RUN. (If both coreboot and seabios run the roms, it can confuse the hardware.)
Copying option rom (size 72192) from 0xfe020000 to c9000 Running option rom at c900:0003 pnp call arg1=60 pmm call arg1=0 pmm00: length=8000 handle=ffffffff flags=6 pmm call arg1=2 pmm02: buffer=7f00000 pmm call arg1=0 pmm00: length=10000 handle=ffffffff flags=6
I guess the boot hangs at this point?
BTW, is this a gPXE rom? It seems to follow a similar pattern of allocating, deallocating, and then allocating a larger chunk.
-Kevin