Re: [SeaBIOS] [PATCH 2/2] fw/pci: map memory and IO regions for multiple pci root buses

[Gerd Hoffmann]

On Mo, 2014-11-24 at 11:47 +0200, Marcel Apfelbaum wrote:
> Removed the assumption that the system has only one primary root bus.
> When mapping memory and IO regions go over all buses, skipping
> secondary and absent buses.

I guess there are qemu patches adding support for multiple pci busses
somewhere?
> for (i = 0; i <= MaxPCIBus; i++) {
>    struct pci_region *r_io = &bus[i].r[PCI_REGION_TYPE_IO];
>    u64 sum = pci_region_sum(r_io);
>    if (bus[i].bus_dev || !sum)
>        continue;
>    sum_pci = ALIGN(sum_pci, sum);
>    sum_free = ALIGN(sum_free, sum);
>    if (sum + sum_pci < 0x4000) {
>        /* traditional region is big enough, use it */
>        r_io->base = 0xc000 + sum_pci;
>        sum_pci += sum;
>    } else if (sum < pci_io_low_end - 0x1000 - sum_free) {
>        /* use the larger region at 0x1000 */
>        r_io->base = 0x1000 + sum_free;
>        sum_free += sum;
>    } else {
>        /* not enough io address space -> error out */
>        return -1;
>    }

Hmm, that assigns the io regions in bus order.  I think it would be
better to integrate this with the packing logic we already have:
regions are sorted by size for best packing.  Regions behind pci bridges
are grouped together.  I think we could group regions belonging to a pci
bus in a simliar way.

cheers,
  Gerd