[SeaBIOS] [PATCH] pci: enable SERR# for error forwording in bridge control register

[Chen Fan]

For PCIe device support AER(Advanced Error Reporting), from the
pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL
can be forwarded from the secondary interface to the primary interface,
only require the SERR# Enable bit in the Bridge Control register is set.

and at the kernel side, we found only _HPP() method can enable
SERR#, So here we want to turn on this bit.

Signed-off-by: Chen Fan 
---
 src/fw/pciinit.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 34279a4..28ed1af 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -310,6 +310,10 @@ static void pci_bios_init_device(struct pci_device *pci)
     /* enable memory mappings */
     pci_config_maskw(bdf, PCI_COMMAND, 0,
                      PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
+    /* enable SERR# for forwording */
+    if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
+        pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
+                         PCI_BRIDGE_CTL_SERR);
 }

static void pci_bios_init_devices(void)