On Thu, Jun 11, 2015 at 08:46:01PM +0300, Marcel Apfelbaum wrote:
On 06/11/2015 07:54 PM, Kevin O'Connor wrote:
On real machines, the firmware assigns the 4 - it's not a physical address; it's a logical address (like all bus numbers in PCI). The firmware might assign a totally different number on the next boot.
Now I am confused. Don't get me wrong, I am not an expert on fw, I hardly try to understand it.
I looked up a real hardware machine and it seemed to me that the extra pci root numbers are provided in the ACPI tables, meaning by the vendor, not the fw. In this case QEMU is the vendor, i440fx is the machine, right?
I am not aware that Seabios/OVMF are deciding the bus numbers for the *PCI roots*.
So, I'm also not an expert on this. It seems to be a fairly esoteric area of PC initialization.
My understanding is that extra PCI roots are configured by coreboot outside of the normal PCI bridge mechanism. They are configured by assigning a base bus number and range (similar to the way PCI bridges are configured). All the PCI roots see all the PCI traffic, but they only forward those requests that fall within their assigned bus range.
On each boot, coreboot might decide to assign a different bus id to the extra roots (for example, if a device with a PCI bridge is inserted and it's bus allocation causes bus ids to shift). Technically, coreboot could even change the order extra buses are assigned bus ids, but doesn't today.
This was seen on several AMD systems - I'm told at least some Intel systems have multiple root buses, but the bus numbers are just hard wired.
They are doing it for the pci-2-pci bridges of course. I saw that Seabios is trying to "guess" the root-buses by going over all the 0-0xff range and probing all the slots, looking for devices. So it expects the hw to be hardwired regarding PCI root buses. Is my understanding incorrect?
SeaBIOS doesn't assign the extra PCI bus numbers on real hardware (nor even regular PCI bridge numbers) - that's all handled by coreboot.
Under coreboot, SeaBIOS scans the PCI buses to figure out what coreboot assigned - it doesn't mean the assignments are hard wired.
-Kevin